Adrian Chadd 358811c4e3 add QCA955x PCIe configuration registers. ...

These are /not/ absolute addresses, as the QCA955x SoC has 2 PCIe RC's
(and 1 PCIe EP.)

2015-03-21 06:00:46 +00:00

..

apb.c

ACK interrupts on the new SoCs.

2015-01-05 02:00:41 +00:00

apbvar.h

The AR71xx has APB interrupts in the MISC registers from 0-7, later

2014-03-16 08:39:46 +00:00

ar71xx_bus_space_reversed.c

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ar71xx_bus_space_reversed.h

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ar71xx_chip.c

Add new features - an MDIO clock, WMAC reset, GMAC reset and ethernet

2013-10-15 01:35:48 +00:00

ar71xx_chip.h

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ar71xx_cpudef.h

Add a GPIO output mux configuration method.

2015-01-03 06:55:58 +00:00

ar71xx_ehci.c

[QCA955x] make the USB EHCI interrupts shareable.

2015-03-02 02:08:43 +00:00

ar71xx_fixup.c

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ar71xx_fixup.h

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ar71xx_gpio.c

Add very initial QCA955x awareness to the GPIO code.

2015-03-01 07:00:34 +00:00

ar71xx_gpiovar.h

Implement GPIO_GET_BUS() method for all GPIO drivers.

2015-01-31 19:32:14 +00:00

ar71xx_macaddr.c

Start fleshing out some MAC address helper functions.

2015-03-15 21:56:12 +00:00

ar71xx_macaddr.h

Start fleshing out some MAC address helper functions.

2015-03-15 21:56:12 +00:00

ar71xx_machdep.c

Follow up to r225617. In order to maximize the re-usability of kernel code

2014-10-16 18:04:43 +00:00

ar71xx_ohci.c

Add 64-bit DMA support in the XHCI controller driver.

2015-01-05 20:22:18 +00:00

ar71xx_pci_bus_space.c

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ar71xx_pci_bus_space.h

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ar71xx_pci.c

Devices that rely on hints or identify routines for discovery need to

2013-10-29 14:07:31 +00:00

ar71xx_setup.c

Add initial Qualcomm Atheros QCA955x SoC support.

2015-01-05 02:06:26 +00:00

ar71xx_setup.h

add QCA955x SoC types.

2015-01-05 01:59:44 +00:00

ar71xx_spi.c

Devices that rely on hints or identify routines for discovery need to

2013-10-29 14:07:31 +00:00

ar71xx_wdog.c

Devices that rely on hints or identify routines for discovery need to

2013-10-29 14:07:31 +00:00

ar71xxreg.h

Add a MII mode for SGMII.

2015-03-02 01:23:59 +00:00

ar91xx_chip.c

Add new features - an MDIO clock, WMAC reset, GMAC reset and ethernet

2013-10-15 01:35:48 +00:00

ar91xx_chip.h

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ar91xxreg.h

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ar724x_chip.c

Add new features - an MDIO clock, WMAC reset, GMAC reset and ethernet

2013-10-15 01:35:48 +00:00

ar724x_chip.h

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ar724x_pci.c

Fix the AR724x PCIe glue to correctly probe the BAR on AR7240 devices.

2014-09-28 07:27:58 +00:00

ar724xreg.h

Note that the AR724x PCIe registers are actually from the PCI_CTRL

2015-03-21 05:59:45 +00:00

ar933x_chip.c

Update the AR933x SoC support to include a few new knobs:

2013-10-15 03:23:08 +00:00

ar933x_chip.h

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ar933x_uart.h

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ar933xreg.h

Add register definitions for the AR933x SoC GMAC (ie, ethernet MAC)

2013-10-14 23:57:12 +00:00

ar934x_chip.c

Add a GPIO output mux configuration method.

2015-01-03 06:55:58 +00:00

ar934x_chip.h

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ar934x_nfcreg.h

Add the AR934x NAND flash controller register definitions.

2014-03-18 12:18:35 +00:00

ar934xreg.h

Add AR934x specific GPIO functions and output MUX configuration.

2015-01-03 06:35:53 +00:00

files.ar71xx

Start fleshing out some MAC address helper functions.

2015-03-15 21:56:12 +00:00

if_arge.c

Use ar71xx_mac_addr_random_init() instead of a hand-rolled random

2015-03-15 21:56:41 +00:00

if_argevar.h

The linux driver code for the MDIO bus does a read-after-write

2015-02-02 17:33:00 +00:00

pcf2123_rtc.c

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pcf2123reg.h

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qca955x_chip.c

Add ethernet MAC DDR flush hookups for QCA955x.

2015-03-04 03:52:50 +00:00

qca955x_chip.h

Add initial Qualcomm Atheros QCA955x SoC support.

2015-01-05 02:06:26 +00:00

qca955xreg.h

add QCA955x PCIe configuration registers.

2015-03-21 06:00:46 +00:00

std.ar71xx

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uart_bus_ar71xx.c

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uart_bus_ar933x.c

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uart_cpu_ar71xx.c

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uart_cpu_ar933x.c

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uart_dev_ar933x.c

Commit some sins in the name of "oh god oh god I don't really want to

2014-07-27 05:44:42 +00:00

uart_dev_ar933x.h

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