3591fea8b0
PCI config access.
350 lines
8.5 KiB
C
350 lines
8.5 KiB
C
/*-
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000, BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/kernel.h>
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#include <sys/mutex.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/pci_cfgreg.h>
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enum {
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CFGMECH_NONE = 0,
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CFGMECH_1,
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CFGMECH_PCIE,
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};
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static uint32_t pci_docfgregread(int bus, int slot, int func, int reg,
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int bytes);
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static int pciereg_cfgread(int bus, unsigned slot, unsigned func,
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unsigned reg, unsigned bytes);
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static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
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unsigned reg, int data, unsigned bytes);
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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static int cfgmech;
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static vm_offset_t pcie_base;
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static int pcie_minbus, pcie_maxbus;
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static uint32_t pcie_badslots;
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static struct mtx pcicfg_mtx;
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static int mcfg_enable = 1;
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TUNABLE_INT("hw.pci.mcfg", &mcfg_enable);
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/*
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* Initialise access to PCI configuration space
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*/
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int
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pci_cfgregopen(void)
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{
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static int once = 0;
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uint64_t pciebar;
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uint16_t did, vid;
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if (!once) {
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mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
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once = 1;
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}
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if (cfgmech != CFGMECH_NONE)
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return (1);
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cfgmech = CFGMECH_1;
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/*
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* Grope around in the PCI config space to see if this is a
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* chipset that is capable of doing memory-mapped config cycles.
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* This also implies that it can do PCIe extended config cycles.
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*/
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/* Check for supported chipsets */
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vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
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did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
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switch (vid) {
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case 0x8086:
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switch (did) {
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case 0x3590:
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case 0x3592:
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/* Intel 7520 or 7320 */
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pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
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pcie_cfgregopen(pciebar, 0, 255);
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break;
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case 0x2580:
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case 0x2584:
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case 0x2590:
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/* Intel 915, 925, or 915GM */
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pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
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pcie_cfgregopen(pciebar, 0, 255);
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break;
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}
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}
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return (1);
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}
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static uint32_t
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pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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if (cfgmech == CFGMECH_PCIE &&
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(bus != 0 || !(1 << slot & pcie_badslots)))
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return (pciereg_cfgread(bus, slot, func, reg, bytes));
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else
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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}
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/*
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* Read configuration space register
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*/
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u_int32_t
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pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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uint32_t line;
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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* 0 in the intline rather than 255 to indicate none. Some use
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* numbers in the range 128-254 to indicate something strange and
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* apparently undocumented anywhere. Assume these are completely bogus
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* and map them to 255, which the rest of the PCI code recognizes as
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* as an invalid IRQ.
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*/
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if (reg == PCIR_INTLINE && bytes == 1) {
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line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
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if (line == 0 || line >= 128)
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line = PCI_INVALID_IRQ;
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return (line);
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}
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return (pci_docfgregread(bus, slot, func, reg, bytes));
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}
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/*
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* Write configuration space register
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*/
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void
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pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
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{
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if (cfgmech == CFGMECH_PCIE &&
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(bus != 0 || !(1 << slot & pcie_badslots)))
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pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
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else
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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}
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/*
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* Configuration space access using direct register operations
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*/
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/* enable configuration space accesses and return data port address */
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static int
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pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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{
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int dataport = 0;
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if (bus <= PCI_BUSMAX && slot < 32 && func <= PCI_FUNCMAX &&
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reg <= PCI_REGMAX && bytes != 3 && (unsigned) bytes <= 4 &&
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(reg & (bytes - 1)) == 0) {
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outl(CONF1_ADDR_PORT, (1 << 31) | (bus << 16) | (slot << 11)
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| (func << 8) | (reg & ~0x03));
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dataport = CONF1_DATA_PORT + (reg & 0x03);
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}
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return (dataport);
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}
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/* disable configuration space accesses */
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static void
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pci_cfgdisable(void)
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{
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/*
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* Do nothing. Writing a 0 to the address port can apparently
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* confuse some bridges and cause spurious access failures.
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*/
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}
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static int
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pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
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{
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int data = -1;
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int port;
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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data = inb(port);
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break;
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case 2:
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data = inw(port);
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break;
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case 4:
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data = inl(port);
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break;
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}
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pci_cfgdisable();
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}
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mtx_unlock_spin(&pcicfg_mtx);
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return (data);
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}
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static void
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pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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{
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int port;
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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outb(port, data);
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break;
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case 2:
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outw(port, data);
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break;
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case 4:
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outl(port, data);
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break;
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}
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pci_cfgdisable();
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}
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mtx_unlock_spin(&pcicfg_mtx);
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}
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int
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pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
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{
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uint32_t val1, val2;
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int slot;
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if (!mcfg_enable)
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return (0);
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if (minbus != 0)
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return (0);
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if (bootverbose)
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printf("PCIe: Memory Mapped configuration base @ 0x%lx\n",
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base);
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/* XXX: We should make sure this really fits into the direct map. */
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pcie_base = (vm_offset_t)pmap_mapdev(base, (maxbus + 1) << 20);
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pcie_minbus = minbus;
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pcie_maxbus = maxbus;
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cfgmech = CFGMECH_PCIE;
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/*
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* On some AMD systems, some of the devices on bus 0 are
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* inaccessible using memory-mapped PCI config access. Walk
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* bus 0 looking for such devices. For these devices, we will
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* fall back to using type 1 config access instead.
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*/
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if (pci_cfgregopen() != 0) {
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for (slot = 0; slot < 32; slot++) {
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val1 = pcireg_cfgread(0, slot, 0, 0, 4);
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if (val1 == 0xffffffff)
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continue;
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val2 = pciereg_cfgread(0, slot, 0, 0, 4);
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if (val2 != val1)
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pcie_badslots |= (1 << slot);
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}
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}
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return (1);
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}
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#define PCIE_VADDR(base, reg, bus, slot, func) \
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((base) + \
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((((bus) & 0xff) << 20) | \
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(((slot) & 0x1f) << 15) | \
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(((func) & 0x7) << 12) | \
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((reg) & 0xfff)))
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static int
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pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
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unsigned bytes)
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{
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volatile vm_offset_t va;
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int data = -1;
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if (bus < pcie_minbus || bus > pcie_maxbus || slot >= 32 ||
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func > PCI_FUNCMAX || reg >= 0x1000)
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return (-1);
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va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
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switch (bytes) {
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case 4:
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data = *(volatile uint32_t *)(va);
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break;
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case 2:
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data = *(volatile uint16_t *)(va);
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break;
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case 1:
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data = *(volatile uint8_t *)(va);
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break;
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}
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return (data);
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}
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static void
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pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
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unsigned bytes)
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{
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volatile vm_offset_t va;
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if (bus < pcie_minbus || bus > pcie_maxbus || slot >= 32 ||
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func > PCI_FUNCMAX || reg >= 0x1000)
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return;
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va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
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switch (bytes) {
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case 4:
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*(volatile uint32_t *)(va) = data;
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break;
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case 2:
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*(volatile uint16_t *)(va) = data;
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break;
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case 1:
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*(volatile uint8_t *)(va) = data;
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break;
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}
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}
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