dc7717a863
It is working on IFC6410 board which has Qualcomm Snapdragon SoC. Approved by: stas (mentor)
569 lines
13 KiB
C
569 lines
13 KiB
C
/*-
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* Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Qualcomm MSM7K/8K uart driver */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kdb.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include <dev/uart/uart_dev_msm.h>
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#include "uart_if.h"
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#define DEF_CLK 7372800
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#define GETREG(bas, reg) \
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bus_space_read_4((bas)->bst, (bas)->bsh, (reg))
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#define SETREG(bas, reg, value) \
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bus_space_write_4((bas)->bst, (bas)->bsh, (reg), (value))
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static int msm_uart_param(struct uart_bas *, int, int, int, int);
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/*
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* Low-level UART interface.
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*/
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static int msm_probe(struct uart_bas *bas);
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static void msm_init(struct uart_bas *bas, int, int, int, int);
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static void msm_term(struct uart_bas *bas);
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static void msm_putc(struct uart_bas *bas, int);
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static int msm_rxready(struct uart_bas *bas);
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static int msm_getc(struct uart_bas *bas, struct mtx *mtx);
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extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
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static int
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msm_uart_param(struct uart_bas *bas, int baudrate, int databits,
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int stopbits, int parity)
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{
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int ulcon;
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ulcon = 0;
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switch (databits) {
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case 5:
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ulcon |= (UART_DM_5_BPS << 4);
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break;
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case 6:
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ulcon |= (UART_DM_6_BPS << 4);
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break;
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case 7:
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ulcon |= (UART_DM_7_BPS << 4);
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break;
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case 8:
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ulcon |= (UART_DM_8_BPS << 4);
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break;
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default:
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return (EINVAL);
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}
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switch (parity) {
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case UART_PARITY_NONE:
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ulcon |= UART_DM_NO_PARITY;
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break;
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case UART_PARITY_ODD:
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ulcon |= UART_DM_ODD_PARITY;
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break;
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case UART_PARITY_EVEN:
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ulcon |= UART_DM_EVEN_PARITY;
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break;
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case UART_PARITY_SPACE:
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ulcon |= UART_DM_SPACE_PARITY;
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break;
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case UART_PARITY_MARK:
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default:
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return (EINVAL);
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}
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switch (stopbits) {
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case 1:
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ulcon |= (UART_DM_SBL_1 << 2);
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break;
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case 2:
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ulcon |= (UART_DM_SBL_2 << 2);
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break;
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default:
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return (EINVAL);
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}
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uart_setreg(bas, UART_DM_MR2, ulcon);
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/* Set 115200 for both TX and RX. */;
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uart_setreg(bas, UART_DM_CSR, UART_DM_CSR_115200);
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uart_barrier(bas);
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return (0);
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}
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struct uart_ops uart_msm_ops = {
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.probe = msm_probe,
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.init = msm_init,
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.term = msm_term,
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.putc = msm_putc,
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.rxready = msm_rxready,
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.getc = msm_getc,
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};
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static int
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msm_probe(struct uart_bas *bas)
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{
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return (0);
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}
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static void
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msm_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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if (bas->rclk == 0)
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bas->rclk = DEF_CLK;
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KASSERT(bas->rclk != 0, ("msm_init: Invalid rclk"));
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/* Set default parameters */
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msm_uart_param(bas, baudrate, databits, stopbits, parity);
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/*
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* Configure UART mode registers MR1 and MR2.
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* Hardware flow control isn't supported.
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*/
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uart_setreg(bas, UART_DM_MR1, 0x0);
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/* Reset interrupt mask register. */
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uart_setreg(bas, UART_DM_IMR, 0);
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/*
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* Configure Tx and Rx watermarks configuration registers.
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* TX watermark value is set to 0 - interrupt is generated when
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* FIFO level is less than or equal to 0.
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*/
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uart_setreg(bas, UART_DM_TFWR, UART_DM_TFW_VALUE);
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/* Set RX watermark value */
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uart_setreg(bas, UART_DM_RFWR, UART_DM_RFW_VALUE);
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/*
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* Configure Interrupt Programming Register.
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* Set initial Stale timeout value.
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*/
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uart_setreg(bas, UART_DM_IPR, UART_DM_STALE_TIMEOUT_LSB);
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/* Disable IRDA mode */
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uart_setreg(bas, UART_DM_IRDA, 0x0);
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/*
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* Configure and enable sim interface if required.
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* Configure hunt character value in HCR register.
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* Keep it in reset state.
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*/
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uart_setreg(bas, UART_DM_HCR, 0x0);
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/* Issue soft reset command */
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SETREG(bas, UART_DM_CR, UART_DM_RESET_TX);
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SETREG(bas, UART_DM_CR, UART_DM_RESET_RX);
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SETREG(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);
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SETREG(bas, UART_DM_CR, UART_DM_RESET_BREAK_INT);
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SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);
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/* Enable/Disable Rx/Tx DM interfaces */
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/* Disable Data Mover for now. */
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uart_setreg(bas, UART_DM_DMEN, 0x0);
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/* Enable transmitter and receiver */
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uart_setreg(bas, UART_DM_CR, UART_DM_CR_RX_ENABLE);
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uart_setreg(bas, UART_DM_CR, UART_DM_CR_TX_ENABLE);
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uart_barrier(bas);
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}
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static void
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msm_term(struct uart_bas *bas)
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{
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/* XXX */
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}
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static void
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msm_putc(struct uart_bas *bas, int c)
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{
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int limit;
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/*
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* Write to NO_CHARS_FOR_TX register the number of characters
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* to be transmitted. However, before writing TX_FIFO must
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* be empty as indicated by TX_READY interrupt in IMR register
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*/
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/*
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* Check if transmit FIFO is empty.
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* If not wait for TX_READY interrupt.
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*/
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limit = 1000;
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if (!(uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXEMT)) {
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while ((uart_getreg(bas, UART_DM_ISR) & UART_DM_TX_READY) == 0
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&& --limit)
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DELAY(4);
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}
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/* FIFO is ready, write number of characters to be written */
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uart_setreg(bas, UART_DM_NO_CHARS_FOR_TX, 1);
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/* Wait till TX FIFO has space */
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while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXRDY) == 0)
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DELAY(4);
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/* TX FIFO has space. Write char */
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SETREG(bas, UART_DM_TF(0), (c & 0xff));
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}
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static int
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msm_rxready(struct uart_bas *bas)
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{
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/* Wait for a character to come ready */
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return ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) ==
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UART_DM_SR_RXRDY);
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}
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static int
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msm_getc(struct uart_bas *bas, struct mtx *mtx)
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{
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int c;
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uart_lock(mtx);
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/* Wait for a character to come ready */
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while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) !=
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UART_DM_SR_RXRDY)
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DELAY(4);
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/* Check for Overrun error. If so reset Error Status */
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if (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_UART_OVERRUN)
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uart_setreg(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);
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/* Read char */
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c = uart_getreg(bas, UART_DM_RF(0));
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uart_unlock(mtx);
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return (c);
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}
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/*
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* High-level UART interface.
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*/
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struct msm_uart_softc {
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struct uart_softc base;
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uint32_t ier;
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};
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static int msm_bus_probe(struct uart_softc *sc);
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static int msm_bus_attach(struct uart_softc *sc);
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static int msm_bus_flush(struct uart_softc *, int);
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static int msm_bus_getsig(struct uart_softc *);
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static int msm_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int msm_bus_ipend(struct uart_softc *);
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static int msm_bus_param(struct uart_softc *, int, int, int, int);
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static int msm_bus_receive(struct uart_softc *);
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static int msm_bus_setsig(struct uart_softc *, int);
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static int msm_bus_transmit(struct uart_softc *);
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static void msm_bus_grab(struct uart_softc *);
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static void msm_bus_ungrab(struct uart_softc *);
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static kobj_method_t msm_methods[] = {
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KOBJMETHOD(uart_probe, msm_bus_probe),
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KOBJMETHOD(uart_attach, msm_bus_attach),
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KOBJMETHOD(uart_flush, msm_bus_flush),
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KOBJMETHOD(uart_getsig, msm_bus_getsig),
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KOBJMETHOD(uart_ioctl, msm_bus_ioctl),
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KOBJMETHOD(uart_ipend, msm_bus_ipend),
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KOBJMETHOD(uart_param, msm_bus_param),
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KOBJMETHOD(uart_receive, msm_bus_receive),
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KOBJMETHOD(uart_setsig, msm_bus_setsig),
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KOBJMETHOD(uart_transmit, msm_bus_transmit),
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KOBJMETHOD(uart_grab, msm_bus_grab),
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KOBJMETHOD(uart_ungrab, msm_bus_ungrab),
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{0, 0 }
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};
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int
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msm_bus_probe(struct uart_softc *sc)
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{
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sc->sc_txfifosz = 64;
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sc->sc_rxfifosz = 64;
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device_set_desc(sc->sc_dev, "Qualcomm HSUART");
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return (0);
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}
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static int
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msm_bus_attach(struct uart_softc *sc)
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{
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struct msm_uart_softc *u = (struct msm_uart_softc *)sc;
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struct uart_bas *bas = &sc->sc_bas;
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sc->sc_hwiflow = 0;
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sc->sc_hwoflow = 0;
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/* Set TX_READY, TXLEV, RXLEV, RXSTALE */
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u->ier = UART_DM_IMR_ENABLED;
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/* Configure Interrupt Mask register IMR */
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uart_setreg(bas, UART_DM_IMR, u->ier);
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return (0);
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}
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/*
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* Write the current transmit buffer to the TX FIFO.
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*/
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static int
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msm_bus_transmit(struct uart_softc *sc)
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{
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struct msm_uart_softc *u = (struct msm_uart_softc *)sc;
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struct uart_bas *bas = &sc->sc_bas;
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int i;
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uart_lock(sc->sc_hwmtx);
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/* Write some data */
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for (i = 0; i < sc->sc_txdatasz; i++) {
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/* Write TX data */
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msm_putc(bas, sc->sc_txbuf[i]);
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uart_barrier(bas);
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}
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/* TX FIFO is empty now, enable TX_READY interrupt */
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u->ier |= UART_DM_TX_READY;
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SETREG(bas, UART_DM_IMR, u->ier);
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uart_barrier(bas);
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/*
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* Inform upper layer that it is transmitting data to hardware,
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* this will be cleared when TXIDLE interrupt occurs.
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*/
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sc->sc_txbusy = 1;
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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static int
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msm_bus_setsig(struct uart_softc *sc, int sig)
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{
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return (0);
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}
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static int
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msm_bus_receive(struct uart_softc *sc)
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{
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struct msm_uart_softc *u = (struct msm_uart_softc *)sc;
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struct uart_bas *bas;
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int c;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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/* Initialize Receive Path and interrupt */
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SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);
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SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_ENABLE);
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u->ier |= UART_DM_RXLEV;
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SETREG(bas, UART_DM_IMR, u->ier);
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/* Loop over until we are full, or no data is available */
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while (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) {
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if (uart_rx_full(sc)) {
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/* No space left in input buffer */
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sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
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break;
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}
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/* Read RX FIFO */
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c = uart_getreg(bas, UART_DM_RF(0));
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uart_barrier(bas);
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uart_rx_put(sc, c);
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}
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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static int
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msm_bus_param(struct uart_softc *sc, int baudrate, int databits,
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int stopbits, int parity)
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{
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int error;
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if (sc->sc_bas.rclk == 0)
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sc->sc_bas.rclk = DEF_CLK;
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KASSERT(sc->sc_bas.rclk != 0, ("msm_init: Invalid rclk"));
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uart_lock(sc->sc_hwmtx);
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error = msm_uart_param(&sc->sc_bas, baudrate, databits, stopbits,
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parity);
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uart_unlock(sc->sc_hwmtx);
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return (error);
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}
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static int
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msm_bus_ipend(struct uart_softc *sc)
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{
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struct msm_uart_softc *u = (struct msm_uart_softc *)sc;
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struct uart_bas *bas = &sc->sc_bas;
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uint32_t isr;
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int ipend;
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uart_lock(sc->sc_hwmtx);
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/* Get ISR status */
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isr = GETREG(bas, UART_DM_MISR);
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ipend = 0;
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/* Uart RX starting, notify upper layer */
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if (isr & UART_DM_RXLEV) {
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u->ier &= ~UART_DM_RXLEV;
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SETREG(bas, UART_DM_IMR, u->ier);
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uart_barrier(bas);
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ipend |= SER_INT_RXREADY;
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}
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/* Stale RX interrupt */
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if (isr & UART_DM_RXSTALE) {
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/* Disable and reset it */
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SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_DISABLE);
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SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);
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uart_barrier(bas);
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ipend |= SER_INT_RXREADY;
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}
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/* TX READY interrupt */
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if (isr & UART_DM_TX_READY) {
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/* Clear TX Ready */
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SETREG(bas, UART_DM_CR, UART_DM_CLEAR_TX_READY);
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/* Disable TX_READY */
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u->ier &= ~UART_DM_TX_READY;
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SETREG(bas, UART_DM_IMR, u->ier);
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uart_barrier(bas);
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if (sc->sc_txbusy != 0)
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ipend |= SER_INT_TXIDLE;
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}
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if (isr & UART_DM_TXLEV) {
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/* TX FIFO is empty */
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u->ier &= ~UART_DM_TXLEV;
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SETREG(bas, UART_DM_IMR, u->ier);
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uart_barrier(bas);
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if (sc->sc_txbusy != 0)
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ipend |= SER_INT_TXIDLE;
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}
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uart_unlock(sc->sc_hwmtx);
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return (ipend);
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}
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static int
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msm_bus_flush(struct uart_softc *sc, int what)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
msm_bus_getsig(struct uart_softc *sc)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
msm_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
|
|
{
|
|
|
|
return (EINVAL);
|
|
}
|
|
|
|
static void
|
|
msm_bus_grab(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
|
|
/*
|
|
* XXX: Turn off all interrupts to enter polling mode. Leave the
|
|
* saved mask alone. We'll restore whatever it was in ungrab.
|
|
*/
|
|
uart_lock(sc->sc_hwmtx);
|
|
SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);
|
|
SETREG(bas, UART_DM_IMR, 0);
|
|
uart_barrier(bas);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
}
|
|
|
|
static void
|
|
msm_bus_ungrab(struct uart_softc *sc)
|
|
{
|
|
struct msm_uart_softc *u = (struct msm_uart_softc *)sc;
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
|
|
/*
|
|
* Restore previous interrupt mask
|
|
*/
|
|
uart_lock(sc->sc_hwmtx);
|
|
SETREG(bas, UART_DM_IMR, u->ier);
|
|
uart_barrier(bas);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
}
|
|
|
|
struct uart_class uart_msm_class = {
|
|
"msm",
|
|
msm_methods,
|
|
sizeof(struct msm_uart_softc),
|
|
.uc_ops = &uart_msm_ops,
|
|
.uc_range = 8,
|
|
.uc_rclk = DEF_CLK,
|
|
};
|