315bbbaa7c
Introduce and use macro to make sure that MCDI buffers allocated on stack are rounded up properly. Submitted by: Gautam Dawar <gdawar at solarflare.com> Sponsored by: Solarflare Communications, Inc. MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D18259
806 lines
22 KiB
C
806 lines
22 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2009-2016 Solarflare Communications Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation are
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* those of the authors and should not be interpreted as representing official
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* policies, either expressed or implied, of the FreeBSD Project.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "efx.h"
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#include "efx_impl.h"
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#if EFSYS_OPT_SIENA
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static void
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siena_phy_decode_cap(
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__in uint32_t mcdi_cap,
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__out uint32_t *maskp)
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{
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uint32_t mask;
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mask = 0;
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN))
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mask |= (1 << EFX_PHY_CAP_10HDX);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN))
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mask |= (1 << EFX_PHY_CAP_10FDX);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN))
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mask |= (1 << EFX_PHY_CAP_100HDX);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN))
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mask |= (1 << EFX_PHY_CAP_100FDX);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN))
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mask |= (1 << EFX_PHY_CAP_1000HDX);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN))
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mask |= (1 << EFX_PHY_CAP_1000FDX);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN))
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mask |= (1 << EFX_PHY_CAP_10000FDX);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN))
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mask |= (1 << EFX_PHY_CAP_PAUSE);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN))
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mask |= (1 << EFX_PHY_CAP_ASYM);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
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mask |= (1 << EFX_PHY_CAP_AN);
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*maskp = mask;
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}
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static void
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siena_phy_decode_link_mode(
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__in efx_nic_t *enp,
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__in uint32_t link_flags,
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__in unsigned int speed,
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__in unsigned int fcntl,
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__out efx_link_mode_t *link_modep,
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__out unsigned int *fcntlp)
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{
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boolean_t fd = !!(link_flags &
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(1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN));
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boolean_t up = !!(link_flags &
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(1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN));
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_NOTE(ARGUNUSED(enp))
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if (!up)
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*link_modep = EFX_LINK_DOWN;
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else if (speed == 10000 && fd)
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*link_modep = EFX_LINK_10000FDX;
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else if (speed == 1000)
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*link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX;
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else if (speed == 100)
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*link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX;
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else if (speed == 10)
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*link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX;
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else
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*link_modep = EFX_LINK_UNKNOWN;
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if (fcntl == MC_CMD_FCNTL_OFF)
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*fcntlp = 0;
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else if (fcntl == MC_CMD_FCNTL_RESPOND)
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*fcntlp = EFX_FCNTL_RESPOND;
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else if (fcntl == MC_CMD_FCNTL_BIDIR)
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*fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
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else {
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EFSYS_PROBE1(mc_pcol_error, int, fcntl);
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*fcntlp = 0;
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}
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}
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void
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siena_phy_link_ev(
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__in efx_nic_t *enp,
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__in efx_qword_t *eqp,
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__out efx_link_mode_t *link_modep)
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{
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efx_port_t *epp = &(enp->en_port);
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unsigned int link_flags;
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unsigned int speed;
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unsigned int fcntl;
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efx_link_mode_t link_mode;
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uint32_t lp_cap_mask;
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/*
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* Convert the LINKCHANGE speed enumeration into mbit/s, in the
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* same way as GET_LINK encodes the speed
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*/
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switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) {
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case MCDI_EVENT_LINKCHANGE_SPEED_100M:
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speed = 100;
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break;
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case MCDI_EVENT_LINKCHANGE_SPEED_1G:
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speed = 1000;
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break;
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case MCDI_EVENT_LINKCHANGE_SPEED_10G:
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speed = 10000;
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break;
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default:
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speed = 0;
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break;
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}
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link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS);
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siena_phy_decode_link_mode(enp, link_flags, speed,
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MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL),
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&link_mode, &fcntl);
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siena_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP),
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&lp_cap_mask);
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/*
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* It's safe to update ep_lp_cap_mask without the driver's port lock
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* because presumably any concurrently running efx_port_poll() is
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* only going to arrive at the same value.
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*
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* ep_fcntl has two meanings. It's either the link common fcntl
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* (if the PHY supports AN), or it's the forced link state. If
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* the former, it's safe to update the value for the same reason as
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* for ep_lp_cap_mask. If the latter, then just ignore the value,
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* because we can race with efx_mac_fcntl_set().
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*/
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epp->ep_lp_cap_mask = lp_cap_mask;
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if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN))
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epp->ep_fcntl = fcntl;
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*link_modep = link_mode;
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}
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__checkReturn efx_rc_t
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siena_phy_power(
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__in efx_nic_t *enp,
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__in boolean_t power)
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{
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efx_rc_t rc;
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if (!power)
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return (0);
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/* Check if the PHY is a zombie */
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if ((rc = siena_phy_verify(enp)) != 0)
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goto fail1;
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enp->en_reset_flags |= EFX_RESET_PHY;
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return (0);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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__checkReturn efx_rc_t
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siena_phy_get_link(
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__in efx_nic_t *enp,
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__out siena_link_state_t *slsp)
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{
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efx_mcdi_req_t req;
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EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LINK_IN_LEN,
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MC_CMD_GET_LINK_OUT_LEN);
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efx_rc_t rc;
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req.emr_cmd = MC_CMD_GET_LINK;
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req.emr_in_buf = payload;
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req.emr_in_length = MC_CMD_GET_LINK_IN_LEN;
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req.emr_out_buf = payload;
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req.emr_out_length = MC_CMD_GET_LINK_OUT_LEN;
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efx_mcdi_execute(enp, &req);
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if (req.emr_rc != 0) {
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rc = req.emr_rc;
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goto fail1;
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}
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if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) {
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rc = EMSGSIZE;
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goto fail2;
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}
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siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP),
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&slsp->sls_adv_cap_mask);
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siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP),
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&slsp->sls_lp_cap_mask);
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siena_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS),
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MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED),
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MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL),
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&slsp->sls_link_mode, &slsp->sls_fcntl);
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#if EFSYS_OPT_LOOPBACK
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/* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS);
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EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD);
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slsp->sls_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE);
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#endif /* EFSYS_OPT_LOOPBACK */
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slsp->sls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0;
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return (0);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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__checkReturn efx_rc_t
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siena_phy_reconfigure(
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__in efx_nic_t *enp)
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{
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efx_port_t *epp = &(enp->en_port);
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efx_mcdi_req_t req;
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EFX_MCDI_DECLARE_BUF(payload,
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MAX(MC_CMD_SET_ID_LED_IN_LEN, MC_CMD_SET_LINK_IN_LEN),
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MAX(MC_CMD_SET_ID_LED_OUT_LEN, MC_CMD_SET_LINK_OUT_LEN));
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uint32_t cap_mask;
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#if EFSYS_OPT_PHY_LED_CONTROL
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unsigned int led_mode;
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#endif
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unsigned int speed;
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efx_rc_t rc;
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req.emr_cmd = MC_CMD_SET_LINK;
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req.emr_in_buf = payload;
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req.emr_in_length = MC_CMD_SET_LINK_IN_LEN;
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req.emr_out_buf = payload;
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req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN;
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cap_mask = epp->ep_adv_cap_mask;
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MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP,
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PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1,
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PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1,
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PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1,
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PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1,
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PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1,
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PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1,
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PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1,
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PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1,
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PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1,
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PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1);
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#if EFSYS_OPT_LOOPBACK
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MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE,
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epp->ep_loopback_type);
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switch (epp->ep_loopback_link_mode) {
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case EFX_LINK_100FDX:
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speed = 100;
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break;
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case EFX_LINK_1000FDX:
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speed = 1000;
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break;
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case EFX_LINK_10000FDX:
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speed = 10000;
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break;
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default:
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speed = 0;
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}
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#else
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MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, MC_CMD_LOOPBACK_NONE);
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speed = 0;
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#endif /* EFSYS_OPT_LOOPBACK */
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MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed);
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#if EFSYS_OPT_PHY_FLAGS
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MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags);
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#else
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MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, 0);
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#endif /* EFSYS_OPT_PHY_FLAGS */
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efx_mcdi_execute(enp, &req);
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if (req.emr_rc != 0) {
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rc = req.emr_rc;
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goto fail1;
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}
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/* And set the blink mode */
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(void) memset(payload, 0, sizeof (payload));
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req.emr_cmd = MC_CMD_SET_ID_LED;
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req.emr_in_buf = payload;
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req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN;
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req.emr_out_buf = payload;
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req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN;
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#if EFSYS_OPT_PHY_LED_CONTROL
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switch (epp->ep_phy_led_mode) {
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case EFX_PHY_LED_DEFAULT:
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led_mode = MC_CMD_LED_DEFAULT;
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break;
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case EFX_PHY_LED_OFF:
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led_mode = MC_CMD_LED_OFF;
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break;
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case EFX_PHY_LED_ON:
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led_mode = MC_CMD_LED_ON;
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break;
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default:
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EFSYS_ASSERT(0);
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led_mode = MC_CMD_LED_DEFAULT;
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}
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MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode);
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#else
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MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT);
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#endif /* EFSYS_OPT_PHY_LED_CONTROL */
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efx_mcdi_execute(enp, &req);
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if (req.emr_rc != 0) {
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rc = req.emr_rc;
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goto fail2;
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}
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return (0);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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__checkReturn efx_rc_t
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siena_phy_verify(
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__in efx_nic_t *enp)
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{
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efx_mcdi_req_t req;
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EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PHY_STATE_IN_LEN,
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MC_CMD_GET_PHY_STATE_OUT_LEN);
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uint32_t state;
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efx_rc_t rc;
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req.emr_cmd = MC_CMD_GET_PHY_STATE;
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req.emr_in_buf = payload;
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req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN;
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req.emr_out_buf = payload;
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req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN;
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efx_mcdi_execute(enp, &req);
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if (req.emr_rc != 0) {
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rc = req.emr_rc;
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goto fail1;
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}
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if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) {
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rc = EMSGSIZE;
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goto fail2;
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}
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state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE);
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if (state != MC_CMD_PHY_STATE_OK) {
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if (state != MC_CMD_PHY_STATE_ZOMBIE)
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EFSYS_PROBE1(mc_pcol_error, int, state);
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rc = ENOTACTIVE;
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goto fail3;
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}
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return (0);
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fail3:
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EFSYS_PROBE(fail3);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
|
|
EFSYS_PROBE1(fail1, efx_rc_t, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
__checkReturn efx_rc_t
|
|
siena_phy_oui_get(
|
|
__in efx_nic_t *enp,
|
|
__out uint32_t *ouip)
|
|
{
|
|
_NOTE(ARGUNUSED(enp, ouip))
|
|
|
|
return (ENOTSUP);
|
|
}
|
|
|
|
#if EFSYS_OPT_PHY_STATS
|
|
|
|
#define SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \
|
|
_mc_record, _efx_record) \
|
|
if ((_vmask) & (1ULL << (_mc_record))) { \
|
|
(_smask) |= (1ULL << (_efx_record)); \
|
|
if ((_stat) != NULL && !EFSYS_MEM_IS_NULL(_esmp)) { \
|
|
efx_dword_t dword; \
|
|
EFSYS_MEM_READD(_esmp, (_mc_record) * 4, &dword);\
|
|
(_stat)[_efx_record] = \
|
|
EFX_DWORD_FIELD(dword, EFX_DWORD_0); \
|
|
} \
|
|
}
|
|
|
|
#define SIENA_SIMPLE_STAT_SET2(_vmask, _esmp, _smask, _stat, _record) \
|
|
SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \
|
|
MC_CMD_ ## _record, \
|
|
EFX_PHY_STAT_ ## _record)
|
|
|
|
void
|
|
siena_phy_decode_stats(
|
|
__in efx_nic_t *enp,
|
|
__in uint32_t vmask,
|
|
__in_opt efsys_mem_t *esmp,
|
|
__out_opt uint64_t *smaskp,
|
|
__inout_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat)
|
|
{
|
|
uint64_t smask = 0;
|
|
|
|
_NOTE(ARGUNUSED(enp))
|
|
|
|
SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI);
|
|
SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP);
|
|
SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT);
|
|
SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT);
|
|
|
|
if (vmask & (1 << MC_CMD_PMA_PMD_SIGNAL)) {
|
|
smask |= ((1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_A) |
|
|
(1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_B) |
|
|
(1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_C) |
|
|
(1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_D));
|
|
if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
|
|
efx_dword_t dword;
|
|
uint32_t sig;
|
|
EFSYS_MEM_READD(esmp, 4 * MC_CMD_PMA_PMD_SIGNAL,
|
|
&dword);
|
|
sig = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
|
|
stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1;
|
|
stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1;
|
|
stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1;
|
|
stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1;
|
|
}
|
|
}
|
|
|
|
SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A,
|
|
EFX_PHY_STAT_SNR_A);
|
|
SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B,
|
|
EFX_PHY_STAT_SNR_B);
|
|
SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C,
|
|
EFX_PHY_STAT_SNR_C);
|
|
SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D,
|
|
EFX_PHY_STAT_SNR_D);
|
|
|
|
SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP);
|
|
SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT);
|
|
SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT);
|
|
SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER);
|
|
SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS);
|
|
|
|
SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP,
|
|
EFX_PHY_STAT_PHY_XS_LINK_UP);
|
|
SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT,
|
|
EFX_PHY_STAT_PHY_XS_RX_FAULT);
|
|
SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT,
|
|
EFX_PHY_STAT_PHY_XS_TX_FAULT);
|
|
SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN,
|
|
EFX_PHY_STAT_PHY_XS_ALIGN);
|
|
|
|
if (vmask & (1 << MC_CMD_PHYXS_SYNC)) {
|
|
smask |= ((1 << EFX_PHY_STAT_PHY_XS_SYNC_A) |
|
|
(1 << EFX_PHY_STAT_PHY_XS_SYNC_B) |
|
|
(1 << EFX_PHY_STAT_PHY_XS_SYNC_C) |
|
|
(1 << EFX_PHY_STAT_PHY_XS_SYNC_D));
|
|
if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
|
|
efx_dword_t dword;
|
|
uint32_t sync;
|
|
EFSYS_MEM_READD(esmp, 4 * MC_CMD_PHYXS_SYNC, &dword);
|
|
sync = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
|
|
stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1;
|
|
stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1;
|
|
stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1;
|
|
stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1;
|
|
}
|
|
}
|
|
|
|
SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP);
|
|
SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE);
|
|
|
|
SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP,
|
|
EFX_PHY_STAT_CL22EXT_LINK_UP);
|
|
|
|
if (smaskp != NULL)
|
|
*smaskp = smask;
|
|
}
|
|
|
|
__checkReturn efx_rc_t
|
|
siena_phy_stats_update(
|
|
__in efx_nic_t *enp,
|
|
__in efsys_mem_t *esmp,
|
|
__inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
|
|
{
|
|
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
|
|
uint32_t vmask = encp->enc_mcdi_phy_stat_mask;
|
|
uint64_t smask;
|
|
efx_mcdi_req_t req;
|
|
EFX_MCDI_DECLARE_BUF(payload, MC_CMD_PHY_STATS_IN_LEN,
|
|
MC_CMD_PHY_STATS_OUT_DMA_LEN);
|
|
efx_rc_t rc;
|
|
|
|
if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_PHY_STATS_SIZE)) {
|
|
rc = EINVAL;
|
|
goto fail1;
|
|
}
|
|
|
|
req.emr_cmd = MC_CMD_PHY_STATS;
|
|
req.emr_in_buf = payload;
|
|
req.emr_in_length = MC_CMD_PHY_STATS_IN_LEN;
|
|
req.emr_out_buf = payload;
|
|
req.emr_out_length = MC_CMD_PHY_STATS_OUT_DMA_LEN;
|
|
|
|
MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_LO,
|
|
EFSYS_MEM_ADDR(esmp) & 0xffffffff);
|
|
MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_HI,
|
|
EFSYS_MEM_ADDR(esmp) >> 32);
|
|
|
|
efx_mcdi_execute(enp, &req);
|
|
|
|
if (req.emr_rc != 0) {
|
|
rc = req.emr_rc;
|
|
goto fail2;
|
|
}
|
|
EFSYS_ASSERT3U(req.emr_out_length, ==, MC_CMD_PHY_STATS_OUT_DMA_LEN);
|
|
|
|
siena_phy_decode_stats(enp, vmask, esmp, &smask, stat);
|
|
EFSYS_ASSERT(smask == encp->enc_phy_stat_mask);
|
|
|
|
return (0);
|
|
|
|
fail2:
|
|
EFSYS_PROBE(fail2);
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, efx_rc_t, rc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
#endif /* EFSYS_OPT_PHY_STATS */
|
|
|
|
#if EFSYS_OPT_BIST
|
|
|
|
__checkReturn efx_rc_t
|
|
siena_phy_bist_start(
|
|
__in efx_nic_t *enp,
|
|
__in efx_bist_type_t type)
|
|
{
|
|
efx_rc_t rc;
|
|
|
|
if ((rc = efx_mcdi_bist_start(enp, type)) != 0)
|
|
goto fail1;
|
|
|
|
return (0);
|
|
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, efx_rc_t, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
static __checkReturn unsigned long
|
|
siena_phy_sft9001_bist_status(
|
|
__in uint16_t code)
|
|
{
|
|
switch (code) {
|
|
case MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY:
|
|
return (EFX_PHY_CABLE_STATUS_BUSY);
|
|
case MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT:
|
|
return (EFX_PHY_CABLE_STATUS_INTERPAIRSHORT);
|
|
case MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT:
|
|
return (EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT);
|
|
case MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN:
|
|
return (EFX_PHY_CABLE_STATUS_OPEN);
|
|
case MC_CMD_POLL_BIST_SFT9001_PAIR_OK:
|
|
return (EFX_PHY_CABLE_STATUS_OK);
|
|
default:
|
|
return (EFX_PHY_CABLE_STATUS_INVALID);
|
|
}
|
|
}
|
|
|
|
__checkReturn efx_rc_t
|
|
siena_phy_bist_poll(
|
|
__in efx_nic_t *enp,
|
|
__in efx_bist_type_t type,
|
|
__out efx_bist_result_t *resultp,
|
|
__out_opt __drv_when(count > 0, __notnull)
|
|
uint32_t *value_maskp,
|
|
__out_ecount_opt(count) __drv_when(count > 0, __notnull)
|
|
unsigned long *valuesp,
|
|
__in size_t count)
|
|
{
|
|
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
|
|
EFX_MCDI_DECLARE_BUF(payload, MC_CMD_POLL_BIST_IN_LEN,
|
|
MCDI_CTL_SDU_LEN_MAX);
|
|
uint32_t value_mask = 0;
|
|
efx_mcdi_req_t req;
|
|
uint32_t result;
|
|
efx_rc_t rc;
|
|
|
|
req.emr_cmd = MC_CMD_POLL_BIST;
|
|
req.emr_in_buf = payload;
|
|
req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN;
|
|
req.emr_out_buf = payload;
|
|
req.emr_out_length = MCDI_CTL_SDU_LEN_MAX;
|
|
|
|
efx_mcdi_execute(enp, &req);
|
|
|
|
if (req.emr_rc != 0) {
|
|
rc = req.emr_rc;
|
|
goto fail1;
|
|
}
|
|
|
|
if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) {
|
|
rc = EMSGSIZE;
|
|
goto fail2;
|
|
}
|
|
|
|
if (count > 0)
|
|
(void) memset(valuesp, '\0', count * sizeof (unsigned long));
|
|
|
|
result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT);
|
|
|
|
/* Extract PHY specific results */
|
|
if (result == MC_CMD_POLL_BIST_PASSED &&
|
|
encp->enc_phy_type == EFX_PHY_SFT9001B &&
|
|
req.emr_out_length_used >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN &&
|
|
(type == EFX_BIST_TYPE_PHY_CABLE_SHORT ||
|
|
type == EFX_BIST_TYPE_PHY_CABLE_LONG)) {
|
|
uint16_t word;
|
|
|
|
if (count > EFX_BIST_PHY_CABLE_LENGTH_A) {
|
|
if (valuesp != NULL)
|
|
valuesp[EFX_BIST_PHY_CABLE_LENGTH_A] =
|
|
MCDI_OUT_DWORD(req,
|
|
POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A);
|
|
value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_A);
|
|
}
|
|
|
|
if (count > EFX_BIST_PHY_CABLE_LENGTH_B) {
|
|
if (valuesp != NULL)
|
|
valuesp[EFX_BIST_PHY_CABLE_LENGTH_B] =
|
|
MCDI_OUT_DWORD(req,
|
|
POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B);
|
|
value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_B);
|
|
}
|
|
|
|
if (count > EFX_BIST_PHY_CABLE_LENGTH_C) {
|
|
if (valuesp != NULL)
|
|
valuesp[EFX_BIST_PHY_CABLE_LENGTH_C] =
|
|
MCDI_OUT_DWORD(req,
|
|
POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C);
|
|
value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_C);
|
|
}
|
|
|
|
if (count > EFX_BIST_PHY_CABLE_LENGTH_D) {
|
|
if (valuesp != NULL)
|
|
valuesp[EFX_BIST_PHY_CABLE_LENGTH_D] =
|
|
MCDI_OUT_DWORD(req,
|
|
POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D);
|
|
value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_D);
|
|
}
|
|
|
|
if (count > EFX_BIST_PHY_CABLE_STATUS_A) {
|
|
if (valuesp != NULL) {
|
|
word = MCDI_OUT_WORD(req,
|
|
POLL_BIST_OUT_SFT9001_CABLE_STATUS_A);
|
|
valuesp[EFX_BIST_PHY_CABLE_STATUS_A] =
|
|
siena_phy_sft9001_bist_status(word);
|
|
}
|
|
value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_A);
|
|
}
|
|
|
|
if (count > EFX_BIST_PHY_CABLE_STATUS_B) {
|
|
if (valuesp != NULL) {
|
|
word = MCDI_OUT_WORD(req,
|
|
POLL_BIST_OUT_SFT9001_CABLE_STATUS_B);
|
|
valuesp[EFX_BIST_PHY_CABLE_STATUS_B] =
|
|
siena_phy_sft9001_bist_status(word);
|
|
}
|
|
value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_B);
|
|
}
|
|
|
|
if (count > EFX_BIST_PHY_CABLE_STATUS_C) {
|
|
if (valuesp != NULL) {
|
|
word = MCDI_OUT_WORD(req,
|
|
POLL_BIST_OUT_SFT9001_CABLE_STATUS_C);
|
|
valuesp[EFX_BIST_PHY_CABLE_STATUS_C] =
|
|
siena_phy_sft9001_bist_status(word);
|
|
}
|
|
value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_C);
|
|
}
|
|
|
|
if (count > EFX_BIST_PHY_CABLE_STATUS_D) {
|
|
if (valuesp != NULL) {
|
|
word = MCDI_OUT_WORD(req,
|
|
POLL_BIST_OUT_SFT9001_CABLE_STATUS_D);
|
|
valuesp[EFX_BIST_PHY_CABLE_STATUS_D] =
|
|
siena_phy_sft9001_bist_status(word);
|
|
}
|
|
value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_D);
|
|
}
|
|
|
|
} else if (result == MC_CMD_POLL_BIST_FAILED &&
|
|
encp->enc_phy_type == EFX_PHY_QLX111V &&
|
|
req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN &&
|
|
count > EFX_BIST_FAULT_CODE) {
|
|
if (valuesp != NULL)
|
|
valuesp[EFX_BIST_FAULT_CODE] =
|
|
MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST);
|
|
value_mask |= 1 << EFX_BIST_FAULT_CODE;
|
|
}
|
|
|
|
if (value_maskp != NULL)
|
|
*value_maskp = value_mask;
|
|
|
|
EFSYS_ASSERT(resultp != NULL);
|
|
if (result == MC_CMD_POLL_BIST_RUNNING)
|
|
*resultp = EFX_BIST_RESULT_RUNNING;
|
|
else if (result == MC_CMD_POLL_BIST_PASSED)
|
|
*resultp = EFX_BIST_RESULT_PASSED;
|
|
else
|
|
*resultp = EFX_BIST_RESULT_FAILED;
|
|
|
|
return (0);
|
|
|
|
fail2:
|
|
EFSYS_PROBE(fail2);
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, efx_rc_t, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
void
|
|
siena_phy_bist_stop(
|
|
__in efx_nic_t *enp,
|
|
__in efx_bist_type_t type)
|
|
{
|
|
/* There is no way to stop BIST on Siena */
|
|
_NOTE(ARGUNUSED(enp, type))
|
|
}
|
|
|
|
#endif /* EFSYS_OPT_BIST */
|
|
|
|
#endif /* EFSYS_OPT_SIENA */
|