488 lines
13 KiB
C
488 lines
13 KiB
C
/*-
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* Copyright (c) 2014 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under
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* the sponsorship of the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/types.h>
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#include <sys/kdb.h>
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#include <sys/pcpu.h>
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#include <sys/systm.h>
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#include <machine/armreg.h>
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#include <machine/cpu.h>
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#include <machine/debug_monitor.h>
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#include <machine/kdb.h>
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#include <machine/param.h>
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#include <ddb/ddb.h>
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#include <ddb/db_sym.h>
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enum dbg_t {
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DBG_TYPE_BREAKPOINT = 0,
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DBG_TYPE_WATCHPOINT = 1,
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};
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static int dbg_watchpoint_num;
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static int dbg_breakpoint_num;
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static int dbg_ref_count_mde[MAXCPU];
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static int dbg_ref_count_kde[MAXCPU];
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/* Watchpoints/breakpoints control register bitfields */
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#define DBG_WATCH_CTRL_LEN_1 (0x1 << 5)
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#define DBG_WATCH_CTRL_LEN_2 (0x3 << 5)
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#define DBG_WATCH_CTRL_LEN_4 (0xf << 5)
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#define DBG_WATCH_CTRL_LEN_8 (0xff << 5)
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#define DBG_WATCH_CTRL_LEN_MASK(x) ((x) & (0xff << 5))
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#define DBG_WATCH_CTRL_EXEC (0x0 << 3)
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#define DBG_WATCH_CTRL_LOAD (0x1 << 3)
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#define DBG_WATCH_CTRL_STORE (0x2 << 3)
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#define DBG_WATCH_CTRL_ACCESS_MASK(x) ((x) & (0x3 << 3))
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/* Common for breakpoint and watchpoint */
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#define DBG_WB_CTRL_EL1 (0x1 << 1)
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#define DBG_WB_CTRL_EL0 (0x2 << 1)
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#define DBG_WB_CTRL_ELX_MASK(x) ((x) & (0x3 << 1))
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#define DBG_WB_CTRL_E (0x1 << 0)
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#define DBG_REG_BASE_BVR 0
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#define DBG_REG_BASE_BCR (DBG_REG_BASE_BVR + 16)
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#define DBG_REG_BASE_WVR (DBG_REG_BASE_BCR + 16)
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#define DBG_REG_BASE_WCR (DBG_REG_BASE_WVR + 16)
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/* Watchpoint/breakpoint helpers */
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#define DBG_WB_WVR "wvr"
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#define DBG_WB_WCR "wcr"
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#define DBG_WB_BVR "bvr"
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#define DBG_WB_BCR "bcr"
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#define DBG_WB_READ(reg, num, val) do { \
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__asm __volatile("mrs %0, dbg" reg #num "_el1" : "=r" (val)); \
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} while (0)
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#define DBG_WB_WRITE(reg, num, val) do { \
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__asm __volatile("msr dbg" reg #num "_el1, %0" :: "r" (val)); \
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} while (0)
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#define READ_WB_REG_CASE(reg, num, offset, val) \
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case (num + offset): \
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DBG_WB_READ(reg, num, val); \
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break
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#define WRITE_WB_REG_CASE(reg, num, offset, val) \
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case (num + offset): \
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DBG_WB_WRITE(reg, num, val); \
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break
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#define SWITCH_CASES_READ_WB_REG(reg, offset, val) \
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READ_WB_REG_CASE(reg, 0, offset, val); \
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READ_WB_REG_CASE(reg, 1, offset, val); \
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READ_WB_REG_CASE(reg, 2, offset, val); \
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READ_WB_REG_CASE(reg, 3, offset, val); \
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READ_WB_REG_CASE(reg, 4, offset, val); \
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READ_WB_REG_CASE(reg, 5, offset, val); \
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READ_WB_REG_CASE(reg, 6, offset, val); \
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READ_WB_REG_CASE(reg, 7, offset, val); \
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READ_WB_REG_CASE(reg, 8, offset, val); \
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READ_WB_REG_CASE(reg, 9, offset, val); \
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READ_WB_REG_CASE(reg, 10, offset, val); \
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READ_WB_REG_CASE(reg, 11, offset, val); \
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READ_WB_REG_CASE(reg, 12, offset, val); \
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READ_WB_REG_CASE(reg, 13, offset, val); \
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READ_WB_REG_CASE(reg, 14, offset, val); \
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READ_WB_REG_CASE(reg, 15, offset, val)
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#define SWITCH_CASES_WRITE_WB_REG(reg, offset, val) \
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WRITE_WB_REG_CASE(reg, 0, offset, val); \
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WRITE_WB_REG_CASE(reg, 1, offset, val); \
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WRITE_WB_REG_CASE(reg, 2, offset, val); \
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WRITE_WB_REG_CASE(reg, 3, offset, val); \
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WRITE_WB_REG_CASE(reg, 4, offset, val); \
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WRITE_WB_REG_CASE(reg, 5, offset, val); \
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WRITE_WB_REG_CASE(reg, 6, offset, val); \
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WRITE_WB_REG_CASE(reg, 7, offset, val); \
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WRITE_WB_REG_CASE(reg, 8, offset, val); \
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WRITE_WB_REG_CASE(reg, 9, offset, val); \
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WRITE_WB_REG_CASE(reg, 10, offset, val); \
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WRITE_WB_REG_CASE(reg, 11, offset, val); \
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WRITE_WB_REG_CASE(reg, 12, offset, val); \
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WRITE_WB_REG_CASE(reg, 13, offset, val); \
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WRITE_WB_REG_CASE(reg, 14, offset, val); \
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WRITE_WB_REG_CASE(reg, 15, offset, val)
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static uint64_t
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dbg_wb_read_reg(int reg, int n)
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{
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uint64_t val = 0;
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switch (reg + n) {
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SWITCH_CASES_READ_WB_REG(DBG_WB_WVR, DBG_REG_BASE_WVR, val);
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SWITCH_CASES_READ_WB_REG(DBG_WB_WCR, DBG_REG_BASE_WCR, val);
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SWITCH_CASES_READ_WB_REG(DBG_WB_BVR, DBG_REG_BASE_BVR, val);
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SWITCH_CASES_READ_WB_REG(DBG_WB_BCR, DBG_REG_BASE_BCR, val);
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default:
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db_printf("trying to read from wrong debug register %d\n", n);
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}
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return val;
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}
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static void
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dbg_wb_write_reg(int reg, int n, uint64_t val)
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{
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switch (reg + n) {
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SWITCH_CASES_WRITE_WB_REG(DBG_WB_WVR, DBG_REG_BASE_WVR, val);
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SWITCH_CASES_WRITE_WB_REG(DBG_WB_WCR, DBG_REG_BASE_WCR, val);
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SWITCH_CASES_WRITE_WB_REG(DBG_WB_BVR, DBG_REG_BASE_BVR, val);
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SWITCH_CASES_WRITE_WB_REG(DBG_WB_BCR, DBG_REG_BASE_BCR, val);
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default:
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db_printf("trying to write to wrong debug register %d\n", n);
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}
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isb();
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}
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void
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kdb_cpu_set_singlestep(void)
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{
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kdb_frame->tf_spsr |= DBG_SPSR_SS;
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WRITE_SPECIALREG(MDSCR_EL1, READ_SPECIALREG(MDSCR_EL1) |
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DBG_MDSCR_SS | DBG_MDSCR_KDE);
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/*
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* Disable breakpoints and watchpoints, e.g. stepping
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* over watched instruction will trigger break exception instead of
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* single-step exception and locks CPU on that instruction for ever.
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*/
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if (dbg_ref_count_mde[PCPU_GET(cpuid)] > 0) {
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WRITE_SPECIALREG(MDSCR_EL1,
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READ_SPECIALREG(MDSCR_EL1) & ~DBG_MDSCR_MDE);
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}
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}
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void
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kdb_cpu_clear_singlestep(void)
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{
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WRITE_SPECIALREG(MDSCR_EL1, READ_SPECIALREG(MDSCR_EL1) &
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~(DBG_MDSCR_SS | DBG_MDSCR_KDE));
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/* Restore breakpoints and watchpoints */
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if (dbg_ref_count_mde[PCPU_GET(cpuid)] > 0) {
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WRITE_SPECIALREG(MDSCR_EL1,
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READ_SPECIALREG(MDSCR_EL1) | DBG_MDSCR_MDE);
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}
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if (dbg_ref_count_kde[PCPU_GET(cpuid)] > 0) {
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WRITE_SPECIALREG(MDSCR_EL1,
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READ_SPECIALREG(MDSCR_EL1) | DBG_MDSCR_KDE);
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}
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}
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static const char *
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dbg_watchtype_str(uint32_t type)
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{
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switch (type) {
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case DBG_WATCH_CTRL_EXEC:
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return ("execute");
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case DBG_WATCH_CTRL_STORE:
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return ("write");
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case DBG_WATCH_CTRL_LOAD:
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return ("read");
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case DBG_WATCH_CTRL_LOAD | DBG_WATCH_CTRL_STORE:
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return ("read/write");
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default:
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return ("invalid");
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}
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}
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static int
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dbg_watchtype_len(uint32_t len)
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{
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switch (len) {
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case DBG_WATCH_CTRL_LEN_1:
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return (1);
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case DBG_WATCH_CTRL_LEN_2:
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return (2);
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case DBG_WATCH_CTRL_LEN_4:
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return (4);
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case DBG_WATCH_CTRL_LEN_8:
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return (8);
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default:
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return (0);
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}
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}
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void
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dbg_show_watchpoint(void)
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{
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uint32_t wcr, len, type;
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uint64_t addr;
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int i;
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db_printf("\nhardware watchpoints:\n");
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db_printf(" watch status type len address symbol\n");
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db_printf(" ----- -------- ---------- --- ------------------ ------------------\n");
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for (i = 0; i < dbg_watchpoint_num; i++) {
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wcr = dbg_wb_read_reg(DBG_REG_BASE_WCR, i);
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if ((wcr & DBG_WB_CTRL_E) != 0) {
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type = DBG_WATCH_CTRL_ACCESS_MASK(wcr);
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len = DBG_WATCH_CTRL_LEN_MASK(wcr);
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addr = dbg_wb_read_reg(DBG_REG_BASE_WVR, i);
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db_printf(" %-5d %-8s %10s %3d 0x%16lx ",
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i, "enabled", dbg_watchtype_str(type),
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dbg_watchtype_len(len), addr);
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db_printsym((db_addr_t)addr, DB_STGY_ANY);
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db_printf("\n");
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} else {
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db_printf(" %-5d disabled\n", i);
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}
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}
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}
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static int
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dbg_find_free_slot(enum dbg_t type)
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{
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u_int max, reg, i;
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switch(type) {
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case DBG_TYPE_BREAKPOINT:
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max = dbg_breakpoint_num;
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reg = DBG_REG_BASE_BCR;
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break;
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case DBG_TYPE_WATCHPOINT:
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max = dbg_watchpoint_num;
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reg = DBG_REG_BASE_WCR;
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break;
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default:
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db_printf("Unsupported debug type\n");
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return (i);
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}
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for (i = 0; i < max; i++) {
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if ((dbg_wb_read_reg(reg, i) & DBG_WB_CTRL_E) == 0)
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return (i);
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}
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return (-1);
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}
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static int
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dbg_find_slot(enum dbg_t type, db_expr_t addr)
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{
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u_int max, reg_addr, reg_ctrl, i;
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switch(type) {
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case DBG_TYPE_BREAKPOINT:
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max = dbg_breakpoint_num;
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reg_addr = DBG_REG_BASE_BVR;
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reg_ctrl = DBG_REG_BASE_BCR;
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break;
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case DBG_TYPE_WATCHPOINT:
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max = dbg_watchpoint_num;
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reg_addr = DBG_REG_BASE_WVR;
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reg_ctrl = DBG_REG_BASE_WCR;
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break;
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default:
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db_printf("Unsupported debug type\n");
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return (i);
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}
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for (i = 0; i < max; i++) {
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if ((dbg_wb_read_reg(reg_addr, i) == addr) &&
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((dbg_wb_read_reg(reg_ctrl, i) & DBG_WB_CTRL_E) != 0))
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return (i);
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}
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return (-1);
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}
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static void
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dbg_enable_monitor(enum dbg_el_t el)
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{
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uint64_t reg_mdcr = 0;
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/*
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* There is no need to have debug monitor on permanently, thus we are
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* refcounting and turn it on only if any of CPU is going to use that.
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*/
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if (atomic_fetchadd_int(&dbg_ref_count_mde[PCPU_GET(cpuid)], 1) == 0)
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reg_mdcr = DBG_MDSCR_MDE;
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if ((el == DBG_FROM_EL1) &&
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atomic_fetchadd_int(&dbg_ref_count_kde[PCPU_GET(cpuid)], 1) == 0)
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reg_mdcr |= DBG_MDSCR_KDE;
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if (reg_mdcr)
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WRITE_SPECIALREG(MDSCR_EL1, READ_SPECIALREG(MDSCR_EL1) | reg_mdcr);
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}
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static void
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dbg_disable_monitor(enum dbg_el_t el)
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{
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uint64_t reg_mdcr = 0;
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if (atomic_fetchadd_int(&dbg_ref_count_mde[PCPU_GET(cpuid)], -1) == 1)
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reg_mdcr = DBG_MDSCR_MDE;
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if ((el == DBG_FROM_EL1) &&
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atomic_fetchadd_int(&dbg_ref_count_kde[PCPU_GET(cpuid)], -1) == 1)
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reg_mdcr |= DBG_MDSCR_KDE;
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if (reg_mdcr)
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WRITE_SPECIALREG(MDSCR_EL1, READ_SPECIALREG(MDSCR_EL1) & ~reg_mdcr);
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}
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int
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dbg_setup_watchpoint(db_expr_t addr, db_expr_t size, enum dbg_el_t el,
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enum dbg_access_t access)
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{
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uint64_t wcr_size, wcr_priv, wcr_access;
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u_int i;
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i = dbg_find_free_slot(DBG_TYPE_WATCHPOINT);
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if (i == -1) {
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db_printf("Can not find slot for watchpoint, max %d"
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" watchpoints supported\n", dbg_watchpoint_num);
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return (i);
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}
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switch(size) {
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case 1:
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wcr_size = DBG_WATCH_CTRL_LEN_1;
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break;
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case 2:
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wcr_size = DBG_WATCH_CTRL_LEN_2;
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break;
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case 4:
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wcr_size = DBG_WATCH_CTRL_LEN_4;
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break;
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case 8:
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wcr_size = DBG_WATCH_CTRL_LEN_8;
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break;
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default:
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db_printf("Unsupported address size for watchpoint\n");
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return (-1);
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}
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switch(el) {
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case DBG_FROM_EL0:
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wcr_priv = DBG_WB_CTRL_EL0;
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break;
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case DBG_FROM_EL1:
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wcr_priv = DBG_WB_CTRL_EL1;
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break;
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default:
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db_printf("Unsupported exception level for watchpoint\n");
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return (-1);
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}
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switch(access) {
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case HW_BREAKPOINT_X:
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wcr_access = DBG_WATCH_CTRL_EXEC;
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break;
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case HW_BREAKPOINT_R:
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wcr_access = DBG_WATCH_CTRL_LOAD;
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break;
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case HW_BREAKPOINT_W:
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wcr_access = DBG_WATCH_CTRL_STORE;
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break;
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case HW_BREAKPOINT_RW:
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wcr_access = DBG_WATCH_CTRL_LOAD | DBG_WATCH_CTRL_STORE;
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break;
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default:
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db_printf("Unsupported exception level for watchpoint\n");
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return (-1);
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}
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dbg_wb_write_reg(DBG_REG_BASE_WVR, i, addr);
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dbg_wb_write_reg(DBG_REG_BASE_WCR, i, wcr_size | wcr_access | wcr_priv |
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DBG_WB_CTRL_E);
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dbg_enable_monitor(el);
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return (0);
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}
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int
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dbg_remove_watchpoint(db_expr_t addr, db_expr_t size, enum dbg_el_t el)
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{
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u_int i;
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i = dbg_find_slot(DBG_TYPE_WATCHPOINT, addr);
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if (i == -1) {
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db_printf("Can not find watchpoint for address 0%lx\n", addr);
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return (i);
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}
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dbg_wb_write_reg(DBG_REG_BASE_WCR, i, 0);
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dbg_disable_monitor(el);
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return (0);
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}
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void
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dbg_monitor_init(void)
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{
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u_int i;
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/* Clear OS lock */
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WRITE_SPECIALREG(OSLAR_EL1, 0);
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/* Find out many breakpoints and watchpoints we can use */
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dbg_watchpoint_num = ((READ_SPECIALREG(ID_AA64DFR0_EL1) >> 20) & 0xf) + 1;
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dbg_breakpoint_num = ((READ_SPECIALREG(ID_AA64DFR0_EL1) >> 12) & 0xf) + 1;
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if (bootverbose && PCPU_GET(cpuid) == 0) {
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db_printf("%d watchpoints and %d breakpoints supported\n",
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dbg_watchpoint_num, dbg_breakpoint_num);
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}
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/*
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* We have limited number of {watch,break}points, each consists of
|
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* two registers:
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* - wcr/bcr regsiter configurates corresponding {watch,break}point
|
|
* behaviour
|
|
* - wvr/bvr register keeps address we are hunting for
|
|
*
|
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* Reset all breakpoints and watchpoints.
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|
*/
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|
for (i = 0; i < dbg_watchpoint_num; ++i) {
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|
dbg_wb_write_reg(DBG_REG_BASE_WCR, i, 0);
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|
dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0);
|
|
}
|
|
|
|
for (i = 0; i < dbg_breakpoint_num; ++i) {
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|
dbg_wb_write_reg(DBG_REG_BASE_BCR, i, 0);
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|
dbg_wb_write_reg(DBG_REG_BASE_BVR, i, 0);
|
|
}
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|
|
|
dbg_enable();
|
|
}
|