4b1df14c60
polarity for a specified IRQ. The intr_config_intr() function wraps this pic method hiding the IRQ to interrupt source lookup. - Add a config_intr() method to the atpic(4) driver that reconfigures the interrupt using the ELCR if possible and returns an error otherwise. - Add a config_intr() method to the apic(4) driver that just logs any requests that would change the existing programming under bootverbose. Currently, the only changes the apic(4) driver receives are due to bugs in the acpi(4) driver and its handling of link devices, hence the reason for such requests currently being ignored. - Have the nexus(4) driver on i386 implement the bus_config_intr() function by calling intr_config_intr().
575 lines
15 KiB
C
575 lines
15 KiB
C
/*-
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* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_auto_eoi.h"
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#include "opt_isa.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <machine/cpufunc.h>
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#include <machine/frame.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/resource.h>
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#include <machine/segments.h>
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#include <dev/ic/i8259.h>
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#include <i386/isa/icu.h>
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#ifdef PC98
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#include <pc98/pc98/pc98.h>
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#else
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#include <i386/isa/isa.h>
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#endif
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#include <isa/isavar.h>
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#define MASTER 0
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#define SLAVE 1
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/*
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* Determine the base master and slave modes not including auto EOI support.
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* All machines that FreeBSD supports use 8086 mode.
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*/
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#ifdef PC98
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/*
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* PC-98 machines do not support auto EOI on the second PIC. Also, it
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* seems that PC-98 machine PICs use buffered mode, and the master PIC
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* uses special fully nested mode.
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*/
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#define BASE_MASTER_MODE (ICW4_SFNM | ICW4_BUF | ICW4_MS | ICW4_8086)
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#define BASE_SLAVE_MODE (ICW4_BUF | ICW4_8086)
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#else
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#define BASE_MASTER_MODE ICW4_8086
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#define BASE_SLAVE_MODE ICW4_8086
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#endif
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/* Enable automatic EOI if requested. */
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#ifdef AUTO_EOI_1
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#define MASTER_MODE (BASE_MASTER_MODE | ICW4_AEOI)
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#else
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#define MASTER_MODE BASE_MASTER_MODE
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#endif
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#ifdef AUTO_EOI_2
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#define SLAVE_MODE (BASE_SLAVE_MODE | ICW4_AEOI)
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#else
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#define SLAVE_MODE BASE_SLAVE_MODE
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#endif
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#define IMEN_MASK(ai) (1 << (ai)->at_irq)
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#define NUM_ISA_IRQS 16
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static void atpic_init(void *dummy);
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unsigned int imen; /* XXX */
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static int using_elcr;
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inthand_t
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IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
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IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
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IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
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IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
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IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
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IDTVEC(atpic_intr15);
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#define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
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#define ATPIC(io, base, eoi, imenptr) \
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{ { atpic_enable_source, atpic_disable_source, (eoi), \
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atpic_enable_intr, atpic_vector, atpic_source_pending, NULL, \
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atpic_resume, atpic_config_intr }, (io), (base), \
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IDT_IO_INTS + (base), (imenptr) }
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#define INTSRC(irq) \
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{ { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
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(irq) % 8 }
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struct atpic {
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struct pic at_pic;
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int at_ioaddr;
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int at_irqbase;
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uint8_t at_intbase;
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uint8_t *at_imen;
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};
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struct atpic_intsrc {
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struct intsrc at_intsrc;
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inthand_t *at_intr;
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int at_irq; /* Relative to PIC base. */
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enum intr_trigger at_trigger;
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u_long at_count;
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u_long at_straycount;
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};
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static void atpic_enable_source(struct intsrc *isrc);
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static void atpic_disable_source(struct intsrc *isrc);
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static void atpic_eoi_master(struct intsrc *isrc);
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static void atpic_eoi_slave(struct intsrc *isrc);
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static void atpic_enable_intr(struct intsrc *isrc);
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static int atpic_vector(struct intsrc *isrc);
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static void atpic_resume(struct intsrc *isrc);
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static int atpic_source_pending(struct intsrc *isrc);
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static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
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enum intr_polarity pol);
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static void i8259_init(struct atpic *pic, int slave);
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static struct atpic atpics[] = {
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ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen),
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ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1)
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};
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static struct atpic_intsrc atintrs[] = {
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INTSRC(0),
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INTSRC(1),
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INTSRC(2),
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INTSRC(3),
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INTSRC(4),
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INTSRC(5),
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INTSRC(6),
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INTSRC(7),
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INTSRC(8),
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INTSRC(9),
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INTSRC(10),
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INTSRC(11),
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INTSRC(12),
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INTSRC(13),
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INTSRC(14),
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INTSRC(15),
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};
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CTASSERT(sizeof(atintrs) / sizeof(struct atpic_intsrc) == NUM_ISA_IRQS);
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static void
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atpic_enable_source(struct intsrc *isrc)
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{
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struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
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struct atpic *ap = (struct atpic *)isrc->is_pic;
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mtx_lock_spin(&icu_lock);
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if (*ap->at_imen & IMEN_MASK(ai)) {
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*ap->at_imen &= ~IMEN_MASK(ai);
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outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
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}
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mtx_unlock_spin(&icu_lock);
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}
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static void
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atpic_disable_source(struct intsrc *isrc)
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{
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struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
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struct atpic *ap = (struct atpic *)isrc->is_pic;
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if (ai->at_trigger == INTR_TRIGGER_EDGE)
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return;
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mtx_lock_spin(&icu_lock);
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*ap->at_imen |= IMEN_MASK(ai);
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outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
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mtx_unlock_spin(&icu_lock);
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}
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static void
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atpic_eoi_master(struct intsrc *isrc)
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{
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KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
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("%s: mismatched pic", __func__));
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#ifndef AUTO_EOI_1
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mtx_lock_spin(&icu_lock);
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outb(atpics[MASTER].at_ioaddr, ICU_EOI);
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mtx_unlock_spin(&icu_lock);
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#endif
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}
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/*
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* The data sheet says no auto-EOI on slave, but it sometimes works.
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* So, if AUTO_EOI_2 is enabled, we use it.
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*/
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static void
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atpic_eoi_slave(struct intsrc *isrc)
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{
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KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
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("%s: mismatched pic", __func__));
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#ifndef AUTO_EOI_2
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mtx_lock_spin(&icu_lock);
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outb(atpics[SLAVE].at_ioaddr, ICU_EOI);
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#ifndef AUTO_EOI_1
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outb(atpics[MASTER].at_ioaddr, ICU_EOI);
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#endif
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mtx_unlock_spin(&icu_lock);
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#endif
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}
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static void
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atpic_enable_intr(struct intsrc *isrc)
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{
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}
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static int
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atpic_vector(struct intsrc *isrc)
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{
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struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
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struct atpic *ap = (struct atpic *)isrc->is_pic;
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return (IRQ(ap, ai));
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}
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static int
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atpic_source_pending(struct intsrc *isrc)
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{
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struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
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struct atpic *ap = (struct atpic *)isrc->is_pic;
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return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
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}
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static void
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atpic_resume(struct intsrc *isrc)
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{
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struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
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struct atpic *ap = (struct atpic *)isrc->is_pic;
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if (ai->at_irq == 0) {
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i8259_init(ap, ap == &atpics[SLAVE]);
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if (ap == &atpics[SLAVE] && using_elcr)
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elcr_resume();
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}
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}
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static int
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atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
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enum intr_polarity pol)
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{
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struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
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u_int vector;
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/* Map conforming values to edge/hi and sanity check the values. */
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if (trig == INTR_TRIGGER_CONFORM)
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trig = INTR_TRIGGER_EDGE;
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if (pol == INTR_POLARITY_CONFORM)
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pol = INTR_POLARITY_HIGH;
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vector = atpic_vector(isrc);
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if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
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(trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
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printf(
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"atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
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vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
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pol == INTR_POLARITY_HIGH ? "high" : "low");
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return (EINVAL);
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}
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/* If there is no change, just return. */
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if (ai->at_trigger == trig)
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return (0);
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/*
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* Certain IRQs can never be level/lo, so don't try to set them
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* that way if asked. At least some ELCR registers ignore setting
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* these bits as well.
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*/
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if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
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trig == INTR_TRIGGER_LEVEL) {
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if (bootverbose)
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printf(
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"atpic: Ignoring invalid level/low configuration for IRQ%u\n",
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vector);
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return (EINVAL);
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}
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if (!using_elcr) {
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if (bootverbose)
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printf("atpic: No ELCR to configure IRQ%u as %s\n",
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vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
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"level/low");
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return (ENXIO);
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}
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if (bootverbose)
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printf("atpic: Programming IRQ%u as %s\n", vector,
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trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
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mtx_lock_spin(&icu_lock);
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elcr_write_trigger(atpic_vector(isrc), trig);
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ai->at_trigger = trig;
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mtx_unlock_spin(&icu_lock);
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return (0);
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}
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static void
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i8259_init(struct atpic *pic, int slave)
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{
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int imr_addr;
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/* Reset the PIC and program with next four bytes. */
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mtx_lock_spin(&icu_lock);
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#ifdef DEV_MCA
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/* MCA uses level triggered interrupts. */
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if (MCA_system)
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outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4 | ICW1_LTIM);
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else
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#endif
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outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
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imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
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/* Start vector. */
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outb(imr_addr, pic->at_intbase);
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/*
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* Setup slave links. For the master pic, indicate what line
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* the slave is configured on. For the slave indicate
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* which line on the master we are connected to.
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*/
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if (slave)
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outb(imr_addr, ICU_SLAVEID); /* my slave id is 7 */
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else
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outb(imr_addr, IRQ_SLAVE); /* slave on line 7 */
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/* Set mode. */
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if (slave)
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outb(imr_addr, SLAVE_MODE);
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else
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outb(imr_addr, MASTER_MODE);
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/* Set interrupt enable mask. */
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outb(imr_addr, *pic->at_imen);
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/* Reset is finished, default to IRR on read. */
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outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
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#ifndef PC98
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/* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
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if (!slave)
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outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
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#endif
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mtx_unlock_spin(&icu_lock);
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}
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void
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atpic_startup(void)
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{
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struct atpic_intsrc *ai;
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int i;
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/* Start off with all interrupts disabled. */
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imen = 0xffff;
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i8259_init(&atpics[MASTER], 0);
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i8259_init(&atpics[SLAVE], 1);
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atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
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/* Install low-level interrupt handlers for all of our IRQs. */
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for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
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if (i == ICU_SLAVEID)
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continue;
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ai->at_intsrc.is_count = &ai->at_count;
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ai->at_intsrc.is_straycount = &ai->at_straycount;
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setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
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ai->at_irq, ai->at_intr, SDT_SYS386IGT, SEL_KPL,
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GSEL(GCODE_SEL, SEL_KPL));
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}
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#ifdef DEV_MCA
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/* For MCA systems, all interrupts are level triggered. */
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if (MCA_system)
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for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
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ai->at_trigger = INTR_TRIGGER_LEVEL;
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else
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#endif
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/*
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* Look for an ELCR. If we find one, update the trigger modes.
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* If we don't find one, assume that IRQs 0, 1, 2, and 13 are
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* edge triggered and that everything else is level triggered.
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* We only use the trigger information to reprogram the ELCR if
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* we have one and as an optimization to avoid masking edge
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* triggered interrupts. For the case that we don't have an ELCR,
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* it doesn't hurt to mask an edge triggered interrupt, so we
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* that is why we assume level trigger for any interrupt that we
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* aren't sure is edge triggered.
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*/
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if (elcr_probe() == 0) {
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using_elcr = 1;
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for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
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ai->at_trigger = elcr_read_trigger(i);
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} else {
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for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
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switch (i) {
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case 0:
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case 1:
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case 2:
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case 8:
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case 13:
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ai->at_trigger = INTR_TRIGGER_EDGE;
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break;
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default:
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ai->at_trigger = INTR_TRIGGER_LEVEL;
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break;
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}
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}
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}
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static void
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atpic_init(void *dummy __unused)
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{
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struct atpic_intsrc *ai;
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int i;
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/* Loop through all interrupt sources and add them. */
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for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
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if (i == ICU_SLAVEID)
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continue;
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intr_register_source(&ai->at_intsrc);
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}
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}
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SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_SECOND + 1, atpic_init, NULL)
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void
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atpic_handle_intr(struct intrframe iframe)
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{
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struct intsrc *isrc;
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KASSERT((u_int)iframe.if_vec < ICU_LEN,
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("unknown int %d\n", iframe.if_vec));
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isrc = &atintrs[iframe.if_vec].at_intsrc;
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/*
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* If we don't have an ithread, see if this is a spurious
|
|
* interrupt.
|
|
*/
|
|
if (isrc->is_ithread == NULL &&
|
|
(iframe.if_vec == 7 || iframe.if_vec == 15)) {
|
|
int port, isr;
|
|
|
|
/*
|
|
* Read the ISR register to see if IRQ 7/15 is really
|
|
* pending. Reset read register back to IRR when done.
|
|
*/
|
|
port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
|
|
mtx_lock_spin(&icu_lock);
|
|
outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
|
|
isr = inb(port);
|
|
outb(port, OCW3_SEL | OCW3_RR);
|
|
mtx_unlock_spin(&icu_lock);
|
|
if ((isr & IRQ7) == 0)
|
|
return;
|
|
}
|
|
intr_execute_handlers(isrc, &iframe);
|
|
}
|
|
|
|
#ifdef DEV_ISA
|
|
/*
|
|
* Bus attachment for the ISA PIC.
|
|
*/
|
|
static struct isa_pnp_id atpic_ids[] = {
|
|
{ 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
|
|
{ 0 }
|
|
};
|
|
|
|
static int
|
|
atpic_probe(device_t dev)
|
|
{
|
|
int result;
|
|
|
|
result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
|
|
if (result <= 0)
|
|
device_quiet(dev);
|
|
return (result);
|
|
}
|
|
|
|
/*
|
|
* We might be granted IRQ 2, as this is typically consumed by chaining
|
|
* between the two PIC components. If we're using the APIC, however,
|
|
* this may not be the case, and as such we should free the resource.
|
|
* (XXX untested)
|
|
*
|
|
* The generic ISA attachment code will handle allocating any other resources
|
|
* that we don't explicitly claim here.
|
|
*/
|
|
static int
|
|
atpic_attach(device_t dev)
|
|
{
|
|
struct resource *res;
|
|
int rid;
|
|
|
|
/* Try to allocate our IRQ and then free it. */
|
|
rid = 0;
|
|
res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
|
|
if (res != NULL)
|
|
bus_release_resource(dev, SYS_RES_IRQ, rid, res);
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t atpic_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, atpic_probe),
|
|
DEVMETHOD(device_attach, atpic_attach),
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t atpic_driver = {
|
|
"atpic",
|
|
atpic_methods,
|
|
1, /* no softc */
|
|
};
|
|
|
|
static devclass_t atpic_devclass;
|
|
|
|
DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
|
|
#ifndef PC98
|
|
DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
|
|
#endif
|
|
|
|
/*
|
|
* Return a bitmap of the current interrupt requests. This is 8259-specific
|
|
* and is only suitable for use at probe time.
|
|
*/
|
|
intrmask_t
|
|
isa_irq_pending(void)
|
|
{
|
|
u_char irr1;
|
|
u_char irr2;
|
|
|
|
irr1 = inb(IO_ICU1);
|
|
irr2 = inb(IO_ICU2);
|
|
return ((irr2 << 8) | irr1);
|
|
}
|
|
#endif /* DEV_ISA */
|