152 lines
5.1 KiB
C
152 lines
5.1 KiB
C
/*
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* Copyright (c) 1996
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* The President and Fellows of Harvard College. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Aaron Brown and
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* Harvard University.
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)cache.h 8.1 (Berkeley) 6/11/93
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* from: NetBSD: cache.h,v 1.3 2000/08/01 00:28:02 eeh Exp
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CACHE_H_
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#define _MACHINE_CACHE_H_
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <dev/ofw/openfirm.h>
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/*
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* Cache diagnostic access definitions.
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*/
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/* ASI offsets for I$ diagnostic access */
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#define ICDA_SET_SHIFT 13
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#define ICDA_SET_MASK (1UL << ICDA_SET_SHIFT)
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#define ICDA_SET(a) (((a) << ICDA_SET_SHIFT) & ICDA_SET_MASK)
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/* I$ tag/valid format */
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#define ICDT_TAG_SHIFT 8
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#define ICDT_TAG_BITS 28
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#define ICDT_TAG_MASK (((1UL << ICDT_TAG_BITS) - 1) << ICDT_TAG_SHIFT)
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#define ICDT_TAG(x) (((x) & ICDT_TAG_MASK) >> ICDT_TAG_SHIFT)
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#define ICDT_VALID (1UL << 36)
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/* D$ tag/valid format */
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#define DCDT_TAG_SHIFT 2
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#define DCDT_TAG_BITS 28
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#define DCDT_TAG_MASK (((1UL << DCDT_TAG_BITS) - 1) << DCDT_TAG_SHIFT)
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#define DCDT_TAG(x) (((x) & DCDT_TAG_MASK) >> DCDT_TAG_SHIFT)
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#define DCDT_VALID_BITS 2
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#define DCDT_VALID_MASK ((1UL << DCDT_VALID_BITS) - 1)
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/* E$ ASI_ECACHE_W/ASI_ECACHE_R address flags */
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#define ECDA_DATA (1UL << 39)
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#define ECDA_TAG (1UL << 40)
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/* E$ tag/state/parity format */
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#define ECDT_TAG_BITS 13
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#define ECDT_TAG_SIZE (1UL << ECDT_TAG_BITS)
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#define ECDT_TAG_MASK (ECDT_TAG_SIZE - 1)
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/*
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* Do two virtual addresses (at which the same page is mapped) form and illegal
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* alias in D$? XXX: should use cache.dc_size here.
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*/
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#define DCACHE_BOUNDARY 0x4000
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#define DCACHE_BMASK (DCACHE_BOUNDARY - 1)
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#define CACHE_BADALIAS(v1, v2) \
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(((v1) & DCACHE_BMASK) != ((v2) & DCACHE_BMASK))
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/*
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* Routines for dealing with the cache.
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*/
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void cache_init(phandle_t); /* turn it on */
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void icache_flush(vm_offset_t, vm_offset_t);
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void icache_inval_phys(vm_offset_t, vm_offset_t);
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void dcache_flush(vm_offset_t, vm_offset_t);
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void dcache_inval(pmap_t, vm_offset_t, vm_offset_t);
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void dcache_inval_phys(vm_offset_t, vm_offset_t);
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void dcache_blast(void);
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void ecache_flush(vm_offset_t, vm_offset_t);
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#if 0
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void ecache_inval_phys(vm_offset_t, vm_offset_t);
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#endif
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void dcache_page_inval(vm_offset_t pa);
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void icache_page_inval(vm_offset_t pa);
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#define DC_TAG_SHIFT 2
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#define DC_VALID_SHIFT 0
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#define DC_TAG_BITS 28
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#define DC_VALID_BITS 2
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#define DC_TAG_MASK ((1 << DC_TAG_BITS) - 1)
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#define DC_VALID_MASK ((1 << DC_VALID_BITS) - 1)
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#define IC_TAG_SHIFT 7
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#define IC_VALID_SHIFT 36
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#define IC_TAG_BITS 28
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#define IC_VALID_BITS 1
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#define IC_TAG_MASK ((1 << IC_TAG_BITS) - 1)
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#define IC_VALID_MASK ((1 << IC_VALID_BITS) - 1)
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/*
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* Cache control information.
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*/
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struct cacheinfo {
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u_int c_enabled; /* true => cache is enabled */
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u_int ic_size; /* instruction cache */
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u_int ic_set;
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u_int ic_l2set;
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u_int ic_assoc;
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u_int ic_linesize;
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u_int dc_size; /* data cache */
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u_int dc_l2size;
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u_int dc_assoc;
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u_int dc_linesize;
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u_int ec_size; /* external cache info */
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u_int ec_assoc;
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u_int ec_l2set;
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u_int ec_linesize;
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u_int ec_l2linesize;
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};
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extern struct cacheinfo cache;
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#endif /* !_MACHINE_CACHE_H_ */
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