Gavin Atkinson 389c8bd51e Align the PCI Express #defines with the style used for the PCI-X ... #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week		2012-09-18 22:04:59 +00:00
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common	- Updated TOE support in the kernel.	2012-06-19 07:34:13 +00:00
sys	- Updated TOE support in the kernel.	2012-06-19 07:34:13 +00:00
ulp	Deal with the case where a syncache entry added by the TOE driver is	2012-08-21 22:23:17 +00:00
bin2h.pl
cxgb_adapter.h	cxgb(4): IPv6 rx/tx hw checksum, IPv6 TSO and LRO too.	2012-06-30 02:11:53 +00:00
cxgb_include.h
cxgb_ioctl.h	Add support for hardware filters to cxgb(4). The T3 chip can inspect	2010-05-05 00:41:40 +00:00
cxgb_main.c	Align the PCI Express #defines with the style used for the PCI-X	2012-09-18 22:04:59 +00:00
cxgb_offload.h	- Updated TOE support in the kernel.	2012-06-19 07:34:13 +00:00
cxgb_osdep.h	Align the PCI Express #defines with the style used for the PCI-X	2012-09-18 22:04:59 +00:00
cxgb_sge.c	cxgb(4): IPv6 rx/tx hw checksum, IPv6 TSO and LRO too.	2012-06-30 02:11:53 +00:00
cxgb_t3fw.c
cxgb_t3fw.h	Update T3 firmware to 7.11.0	2011-03-25 20:53:02 +00:00
t3b_protocol_sram.h
t3b_tp_eeprom.h
t3c_protocol_sram.h
t3c_tp_eeprom.h