b12a863a1e
This implements the "reset controller" side of the clock/reset controller. It's a simple array of registers and bits to set. The register table itself comes from Linux; the rest of the code is a reimplementation. It doesn't yet implement or expose the clock side - I have a lot of reverse engineering to do before that! Reviewed by: andrew, manu, imp Differential Revision: https://reviews.freebsd.org/D32723 Obtained from: Linux (registers)
51 lines
1.9 KiB
C
51 lines
1.9 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __QCOM_GCC_IPQ4018_VAR_H__
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#define __QCOM_GCC_IPQ4018_VAR_H__
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struct qcom_gcc_ipq4018_reset_entry {
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uint32_t reg;
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uint32_t bit;
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};
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struct qcom_gcc_ipq4018_softc {
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device_t dev;
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int reg_rid;
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struct resource *reg;
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struct mtx mtx;
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};
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extern int qcom_gcc_ipq4018_hwreset_assert(device_t dev, intptr_t id,
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bool reset);
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extern int qcom_gcc_ipq4018_hwreset_is_asserted(device_t dev, intptr_t id,
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bool *reset);
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#endif /* __QCOM_GCC_IPQ4018_VAR_H__ */
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