Neel Natu c3498942a5 Restructure the MSR handling so it is entirely handled by processor-specific ... code. There are only a handful of MSRs common between the two so there isn't too much duplicate functionality. The VT-x code has the following types of MSRs: - MSRs that are unconditionally saved/restored on every guest/host context switch (e.g., MSR_GSBASE). - MSRs that are restored to guest values on entry to vmx_run() and saved before returning. This is an optimization for MSRs that are not used in host kernel context (e.g., MSR_KGSBASE). - MSRs that are emulated and every access by the guest causes a trap into the hypervisor (e.g., MSR_IA32_MISC_ENABLE). Reviewed by: grehan		2014-09-20 02:35:21 +00:00
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acpica	Create a separate structure for per-CPU state saved across suspend and	2014-09-06 15:23:28 +00:00
bios	Add missing header needed by free(9).	2012-09-30 15:42:20 +00:00
cpufreq	Pull in r267961 and r267973 again. Fix for issues reported will follow.	2014-06-28 03:56:17 +00:00
include	Restructure the MSR handling so it is entirely handled by processor-specific	2014-09-20 02:35:21 +00:00
iommu	Remove ia64.	2014-07-07 00:27:09 +00:00
isa	atpic: make sure atpic_init is called after IO APIC initialization	2014-08-07 17:00:50 +00:00
pci	Pull in r267961 and r267973 again. Fix for issues reported will follow.	2014-06-28 03:56:17 +00:00
x86	Migrate ie->ie_assign_cpu and associated code to use an int for CPU rather	2014-09-17 17:33:22 +00:00
xen	xen: don't set suspend/resume methods for the PIRQ PIC	2014-09-15 15:15:52 +00:00