361 lines
8.2 KiB
ArmAsm
361 lines
8.2 KiB
ArmAsm
/* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */
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/*-
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* Copyright (C) 1994-1997 Mark Brinicombe
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* Copyright (C) 1994 Brini
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of Brini may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include "assym.s"
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#include <sys/syscall.h>
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#include <machine/asm.h>
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#include <machine/armreg.h>
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#include <machine/pte.h>
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__FBSDID("$FreeBSD$");
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/* What size should this really be ? It is only used by initarm() */
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#define INIT_ARM_STACK_SIZE 2048
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/*
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* This is for kvm_mkdb, and should be the address of the beginning
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* of the kernel text segment (not necessarily the same as kernbase).
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*/
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#define CPWAIT_BRANCH \
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sub pc, pc, #4
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#define CPWAIT(tmp) \
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mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
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mov tmp, tmp /* wait for it to complete */ ;\
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CPWAIT_BRANCH /* branch to next insn */
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.text
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.align 0
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.globl kernbase
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.set kernbase,KERNBASE
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.globl physaddr
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.set physaddr,PHYSADDR
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ENTRY_NP(btext)
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ASENTRY_NP(_start)
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#if defined (FLASHADDR) && defined(LOADERRAMADDR)
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/* Check if we're running from flash. */
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ldr r7, =FLASHADDR
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/*
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* If we're running with MMU disabled, test against the
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* physical address instead.
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*/
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mrc p15, 0, r2, c1, c0, 0
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ands r2, r2, #CPU_CONTROL_MMU_ENABLE
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ldreq r8, =PHYSADDR
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ldrne r8, =LOADERRAMADDR
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cmp r7, r8
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bls flash_lower
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cmp r7, pc
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bhi from_ram
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b do_copy
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flash_lower:
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cmp r8, pc
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bls from_ram
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do_copy:
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ldr r9, =KERNBASE
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adr r1, _start
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ldr r0, Lreal_start
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ldr r2, Lend
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sub r2, r2, r0
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sub r0, r0, r9
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add r0, r0, r8
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mov r4, r0
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bl memcpy
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ldr r0, Lram_offset
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add pc, r4, r0
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Lram_offset: .word from_ram-_C_LABEL(_start)
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from_ram:
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nop
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#endif
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adr r7, Lunmapped
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bic r7, r7, #0xff000000
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orr r7, r7, #PHYSADDR
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disable_mmu:
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/* Disable MMU for a while */
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mrc p15, 0, r2, c1, c0, 0
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bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
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CPU_CONTROL_WBUF_ENABLE)
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bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
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bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
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mcr p15, 0, r2, c1, c0, 0
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nop
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nop
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nop
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mov pc, r7
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Lunmapped:
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#ifdef STARTUP_PAGETABLE_ADDR
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/* build page table from scratch */
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ldr r0, Lstartup_pagetable
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adr r4, mmu_init_table
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b 3f
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2:
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str r3, [r0, r2]
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add r2, r2, #4
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add r3, r3, #(L1_S_SIZE)
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adds r1, r1, #-1
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bhi 2b
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3:
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ldmia r4!, {r1,r2,r3} /* # of sections, VA, PA|attr */
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cmp r1, #0
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adrne r5, 2b
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bicne r5, r5, #0xff000000
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orrne r5, r5, #PHYSADDR
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movne pc, r5
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mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
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mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
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/* Set the Domain Access register. Very important! */
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mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
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mcr p15, 0, r0, c3, c0, 0
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/* Enable MMU */
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #CPU_CONTROL_MMU_ENABLE
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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nop
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CPWAIT(r0)
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#endif
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mmu_done:
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nop
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adr r1, .Lstart
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ldmia r1, {r1, r2, sp} /* Set initial stack and */
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sub r2, r2, r1 /* get zero init data */
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mov r3, #0
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.L1:
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str r3, [r1], #0x0004 /* get zero init data */
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subs r2, r2, #4
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bgt .L1
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ldr pc, .Lvirt_done
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virt_done:
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mov fp, #0 /* trace back starts here */
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bl _C_LABEL(initarm) /* Off we go */
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/* init arm will return the new stack pointer. */
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mov sp, r0
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bl _C_LABEL(mi_startup) /* call mi_startup()! */
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adr r0, .Lmainreturned
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b _C_LABEL(panic)
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/* NOTREACHED */
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#ifdef STARTUP_PAGETABLE_ADDR
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#define MMU_INIT(va,pa,n_sec,attr) \
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.word n_sec ; \
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.word 4*((va)>>L1_S_SHIFT) ; \
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.word (pa)|(attr) ;
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Lvirtaddr:
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.word KERNVIRTADDR
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Lphysaddr:
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.word KERNPHYSADDR
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Lreal_start:
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.word _start
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Lend:
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.word _edata
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Lstartup_pagetable:
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.word STARTUP_PAGETABLE_ADDR
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mmu_init_table:
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/* fill all table VA==PA */
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/* map SDRAM VA==PA, WT cacheable */
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MMU_INIT(PHYSADDR, PHYSADDR , 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
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/* map VA 0xc0000000..0xc3ffffff to PA */
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MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
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.word 0 /* end of table */
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#endif
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.Lstart:
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.word _edata
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.word _end
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.word svcstk + INIT_ARM_STACK_SIZE
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#if defined(FLASHADDR) && defined(LOADERRAMADDR)
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.L_arm_memcpy:
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.word _C_LABEL(_arm_memcpy)
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#endif
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.Lvirt_done:
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.word virt_done
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.Lmainreturned:
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.asciz "main() returned"
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.align 0
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.bss
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svcstk:
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.space INIT_ARM_STACK_SIZE
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.text
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.align 0
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.Lcpufuncs:
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.word _C_LABEL(cpufuncs)
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ENTRY_NP(cpu_halt)
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mrs r2, cpsr
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bic r2, r2, #(PSR_MODE)
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orr r2, r2, #(PSR_SVC32_MODE)
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orr r2, r2, #(I32_bit | F32_bit)
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msr cpsr_all, r2
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ldr r4, .Lcpu_reset_address
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ldr r4, [r4]
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ldr r0, .Lcpufuncs
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mov lr, pc
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ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
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/*
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* Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's
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* necessary.
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*/
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ldr r1, .Lcpu_reset_needs_v4_MMU_disable
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ldr r1, [r1]
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cmp r1, #0
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mov r2, #0
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/*
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* MMU & IDC off, 32 bit program & data space
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* Hurl ourselves into the ROM
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*/
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mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
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mcr 15, 0, r0, c1, c0, 0
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mcrne 15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
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mov pc, r4
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/*
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* _cpu_reset_address contains the address to branch to, to complete
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* the cpu reset after turning the MMU off
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* This variable is provided by the hardware specific code
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*/
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.Lcpu_reset_address:
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.word _C_LABEL(cpu_reset_address)
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/*
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* cpu_reset_needs_v4_MMU_disable contains a flag that signals if the
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* v4 MMU disable instruction needs executing... it is an illegal instruction
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* on f.e. ARM6/7 that locks up the computer in an endless illegal
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* instruction / data-abort / reset loop.
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*/
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.Lcpu_reset_needs_v4_MMU_disable:
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.word _C_LABEL(cpu_reset_needs_v4_MMU_disable)
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#ifdef IPKDB
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/*
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* Execute(inst, psr, args, sp)
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*
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* Execute INSTruction with PSR and ARGS[0] - ARGS[3] making
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* available stack at SP for next undefined instruction trap.
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*
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* Move the instruction onto the stack and jump to it.
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*/
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ENTRY_NP(Execute)
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mov ip, sp
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stmfd sp!, {r2, r4-r7, fp, ip, lr, pc}
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sub fp, ip, #4
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mov ip, r3
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ldr r7, .Lreturn
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stmfd sp!, {r0, r7}
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adr r7, #.LExec
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mov r5, r1
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mrs r4, cpsr
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ldmia r2, {r0-r3}
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mov r6, sp
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mov sp, ip
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msr cpsr_all, r5
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mov pc, r6
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.LExec:
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mrs r5, cpsr
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/* XXX Cannot switch thus easily back from user mode */
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msr cpsr_all, r4
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add sp, r6, #8
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ldmfd sp!, {r6}
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stmia r6, {r0-r3}
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mov r0, r5
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ldmdb fp, {r4-r7, fp, sp, pc}
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.Lreturn:
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mov pc, r7
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#endif
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/*
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* setjump + longjmp
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*/
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ENTRY(setjmp)
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stmia r0, {r4-r14}
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mov r0, #0x00000000
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RET
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ENTRY(longjmp)
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ldmia r0, {r4-r14}
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mov r0, #0x00000001
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RET
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.data
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.global _C_LABEL(esym)
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_C_LABEL(esym): .word _C_LABEL(end)
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ENTRY_NP(abort)
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b _C_LABEL(abort)
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ENTRY_NP(sigcode)
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mov r0, sp
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swi SYS_sigreturn
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/* Well if that failed we better exit quick ! */
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swi SYS_exit
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b . - 8
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.align 0
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.global _C_LABEL(esigcode)
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_C_LABEL(esigcode):
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.data
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.global szsigcode
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szsigcode:
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.long esigcode-sigcode
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/* End of locore.S */
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