42b919d4a6
register stack. There's nothing really wrong with flushing before putting the RSE in enforced lazy mode, provided you don't depend on ar.bspstore being equal to ar.bsp when the RSE has been put in enforced lazy more. The small window between the flush and setting the RSE may be sufficient to have the RSE eagerly increase the dirty region (and hence cause ar.bspstore != ar.bsp) or have an interrupt that may even get the laziest RSE to do something. Anyway: we don't depend on ar.bspstore being equal to ar.bsp, so nothing was and is broken. But the code was non-intuitive and easily confuses. This is a source of future bugs. Note: the advantage of not depending on ar.bspstore is that there's some recilience against an interrupted flushrs. Clobbering is limited to stacked register contents only, not to RSE address clobbering. Approved: re@ (blanket)
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