391 lines
9.7 KiB
C
391 lines
9.7 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*-
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*-
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* Additional Copyright (c) 1998 by Andrew Gallatin for Duke University
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/interrupt.h>
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#include <alpha/pci/apecsreg.h>
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#include <alpha/pci/apecsvar.h>
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#include <alpha/isa/isavar.h>
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#include <machine/cpuconf.h>
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#include <machine/intr.h>
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#include <machine/intrcnt.h>
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#include <machine/md_var.h>
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#include <machine/resource.h>
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#include <machine/rpb.h>
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#include <machine/sgmap.h>
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#include <machine/swiz.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa)
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static devclass_t apecs_devclass;
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static device_t apecs0; /* XXX only one for now */
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struct apecs_softc {
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vm_offset_t dmem_base; /* dense memory */
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vm_offset_t smem_base; /* sparse memory */
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vm_offset_t io_base; /* dense i/o */
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vm_offset_t cfg0_base; /* dense pci0 config */
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vm_offset_t cfg1_base; /* dense pci1 config */
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};
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#define APECS_SOFTC(dev) (struct apecs_softc*) device_get_softc(dev)
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static alpha_chipset_read_hae_t apecs_read_hae;
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static alpha_chipset_write_hae_t apecs_write_hae;
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static alpha_chipset_t apecs_swiz_chipset = {
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apecs_read_hae,
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apecs_write_hae,
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};
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/*
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* Memory functions.
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*
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* XXX linux does 32-bit reads/writes via dense space. This doesn't
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* appear to work for devices behind a ppb. I'm using sparse
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* accesses & they appear to work just fine everywhere.
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*/
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static u_int32_t apecs_hae_mem;
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#define REG1 (1UL << 24)
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static u_int32_t
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apecs_set_hae_mem(void *arg, u_int32_t pa)
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{
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int s;
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u_int32_t msb;
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if (pa >= REG1){
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msb = pa & 0xf8000000;
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pa -= msb;
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s = splhigh();
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if (msb != apecs_hae_mem) {
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apecs_hae_mem = msb;
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REGVAL(EPIC_HAXR1) = apecs_hae_mem;
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alpha_mb();
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apecs_hae_mem = REGVAL(EPIC_HAXR1);
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}
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splx(s);
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}
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return pa;
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}
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static u_int64_t
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apecs_read_hae(void)
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{
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return apecs_hae_mem & 0xf8000000;
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}
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static void
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apecs_write_hae(u_int64_t hae)
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{
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u_int32_t pa = hae;
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apecs_set_hae_mem(0, pa);
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}
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static int apecs_probe(device_t dev);
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static int apecs_attach(device_t dev);
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static int apecs_setup_intr(device_t dev, device_t child,
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struct resource *irq, int flags,
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driver_intr_t *intr, void *arg, void **cookiep);
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static int apecs_teardown_intr(device_t dev, device_t child,
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struct resource *irq, void *cookie);
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static device_method_t apecs_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, apecs_probe),
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DEVMETHOD(device_attach, apecs_attach),
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/* Bus interface */
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DEVMETHOD(bus_setup_intr, apecs_setup_intr),
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DEVMETHOD(bus_teardown_intr, apecs_teardown_intr),
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{ 0, 0 }
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};
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static driver_t apecs_driver = {
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"apecs",
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apecs_methods,
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sizeof(struct apecs_softc),
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};
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#define APECS_SGMAP_BASE (8*1024*1024)
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#define APECS_SGMAP_SIZE (8*1024*1024)
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static void
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apecs_sgmap_invalidate(void)
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{
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alpha_mb();
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REGVAL(EPIC_TBIA) = 0;
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alpha_mb();
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}
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static void
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apecs_sgmap_map(void *arg, bus_addr_t ba, vm_offset_t pa)
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{
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u_int64_t *sgtable = arg;
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int index = alpha_btop(ba - APECS_SGMAP_BASE);
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if (pa) {
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if (pa > (1L<<32))
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panic("apecs_sgmap_map: can't map address 0x%lx", pa);
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sgtable[index] = ((pa >> 13) << 1) | 1;
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} else {
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sgtable[index] = 0;
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}
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alpha_mb();
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apecs_sgmap_invalidate();
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}
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static void
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apecs_init_sgmap(void)
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{
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void *sgtable;
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/*
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* First setup Window 0 to map 8Mb to 16Mb with an
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* sgmap. Allocate the map aligned to a 32 boundary.
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*/
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REGVAL(EPIC_PCI_BASE_1) = APECS_SGMAP_BASE |
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EPIC_PCI_BASE_SGEN | EPIC_PCI_BASE_WENB;
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alpha_mb();
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REGVAL(EPIC_PCI_MASK_1) = EPIC_PCI_MASK_8M;
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alpha_mb();
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sgtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
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0, (1L<<34),
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32*1024, (1L<<34));
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if (!sgtable)
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panic("apecs_init_sgmap: can't allocate page table");
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REGVAL(EPIC_TBASE_1) =
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(pmap_kextract((vm_offset_t) sgtable) >> EPIC_TBASE_SHIFT);
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chipset.sgmap = sgmap_map_create(APECS_SGMAP_BASE,
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APECS_SGMAP_BASE + APECS_SGMAP_SIZE,
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apecs_sgmap_map, sgtable);
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chipset.pci_sgmap = NULL;
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chipset.dmsize = 1UL * 1024UL * 1024UL * 1024UL;
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chipset.dmoffset = 1UL * 1024UL * 1024UL * 1024UL;
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}
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void
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apecs_init()
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{
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static int initted = 0;
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static struct swiz_space io_space, mem_space;
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if (initted) return;
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initted = 1;
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swiz_init_space(&io_space, KV(APECS_PCI_SIO));
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swiz_init_space_hae(&mem_space, KV(APECS_PCI_SPARSE),
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apecs_set_hae_mem, 0);
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busspace_isa_io = (struct alpha_busspace *) &io_space;
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busspace_isa_mem = (struct alpha_busspace *) &mem_space;
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chipset = apecs_swiz_chipset;
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if (platform.pci_intr_init)
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platform.pci_intr_init();
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}
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static int
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apecs_probe(device_t dev)
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{
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int memwidth;
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if (apecs0)
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return ENXIO;
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apecs0 = dev;
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memwidth = (REGVAL(COMANCHE_GCR) & COMANCHE_GCR_WIDEMEM) != 0 ? 128 : 64;
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if(memwidth == 64){
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device_set_desc(dev, "DECchip 21071 Core Logic chipset");
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} else {
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device_set_desc(dev, "DECchip 21072 Core Logic chipset");
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}
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apecs_hae_mem = REGVAL(EPIC_HAXR1);
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isa_init_intr();
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apecs_init_sgmap();
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device_add_child(dev, "pcib", 0);
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return 0;
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}
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static int
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apecs_attach(device_t dev)
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{
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struct apecs_softc* sc = APECS_SOFTC(dev);
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apecs_init();
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sc->dmem_base = APECS_PCI_DENSE;
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sc->smem_base = APECS_PCI_SPARSE;
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sc->io_base = APECS_PCI_SIO;
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sc->cfg0_base = KV(APECS_PCI_CONF);
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sc->cfg1_base = 0;
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set_iointr(alpha_dispatch_intr);
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snprintf(chipset_type, sizeof(chipset_type), "apecs");
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chipset_bwx = 0;
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chipset_ports = APECS_PCI_SIO;
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chipset_memory = APECS_PCI_SPARSE;
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chipset_dense = APECS_PCI_DENSE;
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chipset_hae_mask = EPIC_HAXR1_EADDR;
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bus_generic_attach(dev);
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return 0;
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}
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static void
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apecs_disable_intr(uintptr_t vector)
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{
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int irq;
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irq = (vector - 0x900) >> 4;
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mtx_lock_spin(&icu_lock);
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platform.pci_intr_disable(irq);
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mtx_unlock_spin(&icu_lock);
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}
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static void
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apecs_enable_intr(uintptr_t vector)
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{
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int irq;
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irq = (vector - 0x900) >> 4;
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mtx_lock_spin(&icu_lock);
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platform.pci_intr_enable(irq);
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mtx_unlock_spin(&icu_lock);
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}
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static int
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apecs_setup_intr(device_t dev, device_t child,
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struct resource *irq, int flags,
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driver_intr_t *intr, void *arg, void **cookiep)
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{
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int error, start;
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start = rman_get_start(irq);
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/*
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* the avanti routes interrupts through the isa interrupt
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* controller, so we need to special case it
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*/
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if(hwrpb->rpb_type == ST_DEC_2100_A50)
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return isa_setup_intr(dev, child, irq, flags,
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intr, arg, cookiep);
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error = rman_activate_resource(irq);
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if (error)
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return error;
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error = alpha_setup_intr(device_get_nameunit(child ? child : dev),
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0x900 + (start << 4), intr, arg, flags, cookiep,
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&intrcnt[INTRCNT_EB64PLUS_IRQ + start],
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apecs_disable_intr, apecs_enable_intr);
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if (error)
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return error;
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/* Enable PCI interrupt */
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mtx_lock_spin(&icu_lock);
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platform.pci_intr_enable(start);
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mtx_unlock_spin(&icu_lock);
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device_printf(child, "interrupting at APECS irq %d\n", start);
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return 0;
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}
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static int
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apecs_teardown_intr(device_t dev, device_t child,
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struct resource *irq, void *cookie)
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{
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/*
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* the avanti routes interrupts through the isa interrupt
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* controller, so we need to special case it
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*/
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if(hwrpb->rpb_type == ST_DEC_2100_A50)
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return isa_teardown_intr(dev, child, irq, cookie);
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alpha_teardown_intr(cookie);
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return rman_deactivate_resource(irq);
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}
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DRIVER_MODULE(apecs, root, apecs_driver, apecs_devclass, 0, 0);
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