47351d2774
was needed to make attach/detach of devices work, which is needed for the PCCARD support. (PCCARD support is still not working though, more to come on that) Support the CMD646 chip which is used on many alphas, sadly only in WDMA2 mode, as the silicon is broken beyond belief for UDMA modes. Lots of cosmetic fixes here and there. Sorry for the size of this megapatchfromhell but it was not possible otherwise... newbus patches based on work from: dfr (Doug Rabson)
753 lines
23 KiB
C
753 lines
23 KiB
C
/*-
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* Copyright (c) 1998,1999,2000 Søren Schmidt
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "pci.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/buf.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <sys/disk.h>
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#include <sys/devicestat.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#if NPCI > 0
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#include <pci/pcivar.h>
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#endif
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-disk.h>
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#if NPCI > 0
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/* prototypes */
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static void promise_timing(struct ata_softc *, int32_t, int32_t);
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static void hpt366_timing(struct ata_softc *, int32_t, int32_t);
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/* misc defines */
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#ifdef __alpha__
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#undef vtophys
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#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
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#endif
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void
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ata_dmainit(struct ata_softc *scp, int32_t device,
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int32_t apiomode, int32_t wdmamode, int32_t udmamode)
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{
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device_t parent = device_get_parent(scp->dev);
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int32_t devno = (scp->unit << 1) + ATA_DEV(device);
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int32_t error;
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/* set our most pessimistic default mode */
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scp->mode[ATA_DEV(device)] = ATA_PIO;
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if (!scp->bmaddr)
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return;
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/* if simplex controller, only allow DMA on primary channel */
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if (scp->unit == 1) {
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outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) &
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(ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
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if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
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ata_printf(scp, device, "simplex device, DMA on primary only\n");
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return;
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}
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}
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if (!scp->dmatab[ATA_DEV(device)]) {
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void *dmatab;
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if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT)))
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return;
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if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
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(((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
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ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n");
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free(dmatab, M_DEVBUF);
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return;
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}
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scp->dmatab[ATA_DEV(device)] = dmatab;
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}
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switch (scp->chiptype) {
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case 0x71118086: /* Intel PIIX4 */
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case 0x71998086: /* Intel PIIX4e */
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case 0x24118086: /* Intel ICH */
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case 0x24218086: /* Intel ICH0 */
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if (udmamode >= 2) {
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int32_t mask48, new48;
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
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(error) ? "failed" : "success",
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(scp->chiptype == 0x24118086) ? "ICH" :
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(scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
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if (!error) {
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mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
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new48 = (1 << devno) + (2 << (16 + (devno << 2)));
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pci_write_config(parent, 0x48,
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(pci_read_config(parent, 0x48, 4) &
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~mask48) | new48, 4);
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scp->mode[ATA_DEV(device)] = ATA_UDMA2;
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return;
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}
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}
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/* FALLTHROUGH */
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case 0x70108086: /* Intel PIIX3 */
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if (wdmamode >= 2 && apiomode >= 4) {
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int32_t mask40, new40, mask44, new44;
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/* if SITRE not set doit for both channels */
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if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){
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new40 = pci_read_config(parent, 0x40, 4);
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new44 = pci_read_config(parent, 0x44, 4);
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if (!(new40 & 0x00004000)) {
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new44 &= ~0x0000000f;
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new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
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}
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if (!(new40 & 0x40000000)) {
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new44 &= ~0x000000f0;
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new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
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}
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new40 |= 0x40004000;
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pci_write_config(parent, 0x40, new40, 4);
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pci_write_config(parent, 0x44, new44, 4);
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}
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
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(error) ? "failed" : "success",
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(scp->chiptype == 0x70108086) ? "PIIX3" :
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(scp->chiptype == 0x24118086) ? "ICH" :
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(scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
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if (!error) {
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if (device == ATA_MASTER) {
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mask40 = 0x0000330f;
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new40 = 0x00002307;
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mask44 = 0;
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new44 = 0;
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}
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else {
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mask40 = 0x000000f0;
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new40 = 0x00000070;
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mask44 = 0x0000000f;
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new44 = 0x0000000b;
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}
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if (scp->unit) {
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mask40 <<= 16;
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new40 <<= 16;
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mask44 <<= 4;
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new44 <<= 4;
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}
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pci_write_config(parent, 0x40,
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(pci_read_config(parent, 0x40, 4) & ~mask40)|
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new40, 4);
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pci_write_config(parent, 0x44,
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(pci_read_config(parent, 0x44, 4) & ~mask44)|
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new44, 4);
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scp->mode[ATA_DEV(device)] = ATA_WDMA2;
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return;
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}
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}
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/* we could set PIO mode timings, but we assume the BIOS did that */
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break;
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case 0x12308086: /* Intel PIIX */
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if (wdmamode >= 2 && apiomode >= 4) {
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int32_t word40;
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word40 = pci_read_config(parent, 0x40, 4);
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word40 >>= scp->unit * 16;
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/* Check for timing config usable for DMA on controller */
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if (!((word40 & 0x3300) == 0x2300 &&
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((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
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break;
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device,
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"%s setting up WDMA2 mode on PIIX chip\n",
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(error) ? "failed" : "success");
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if (!error) {
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scp->mode[ATA_DEV(device)] = ATA_WDMA2;
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return;
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}
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}
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break;
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case 0x522910b9: /* AcerLabs Aladdin IV/V */
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/* the Aladdin doesn't support ATAPI DMA on both master & slave */
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if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
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ata_printf(scp, device,
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"Aladdin: two atapi devices on this channel, no DMA\n");
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break;
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}
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if (udmamode >= 2) {
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int32_t word54 = pci_read_config(parent, 0x54, 4);
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device,
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"%s setting up UDMA2 mode on Aladdin chip\n",
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(error) ? "failed" : "success");
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if (!error) {
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word54 |= 0x5555;
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word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2)));
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pci_write_config(parent, 0x54, word54, 4);
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pci_write_config(parent, 0x53,
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pci_read_config(parent, 0x53, 1) | 0x03, 1);
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scp->flags |= ATA_ATAPI_DMA_RO;
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scp->mode[ATA_DEV(device)] = ATA_UDMA2;
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return;
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}
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}
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if (wdmamode >= 2 && apiomode >= 4) {
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device,
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"%s setting up WDMA2 mode on Aladdin chip\n",
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(error) ? "failed" : "success");
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if (!error) {
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pci_write_config(parent, 0x53,
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pci_read_config(parent, 0x53, 1) | 0x03, 1);
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scp->flags |= ATA_ATAPI_DMA_RO;
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scp->mode[ATA_DEV(device)] = ATA_WDMA2;
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return;
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}
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}
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/* we could set PIO mode timings, but we assume the BIOS did that */
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break;
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case 0x06861106: /* VIA 82C686 */
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if (udmamode >= 4) {
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device,
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"%s setting up UDMA4 mode on VIA chip\n",
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(error) ? "failed" : "success");
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if (!error) {
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pci_write_config(parent, 0x53 - devno, 0xe8, 1);
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scp->mode[ATA_DEV(device)] = ATA_UDMA4;
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return;
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}
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}
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if (udmamode >= 2) {
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device,
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"%s setting up UDMA2 mode on VIA chip\n",
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(error) ? "failed" : "success");
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if (!error) {
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pci_write_config(parent, 0x53 - devno, 0xea, 1);
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scp->mode[ATA_DEV(device)] = ATA_UDMA2;
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return;
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}
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}
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goto via_generic;
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case 0x74091022: /* AMD 756 */
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if (udmamode >= 4) {
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device,
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"%s setting up UDMA4 mode on AMD chip\n",
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(error) ? "failed" : "success");
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if (!error) {
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pci_write_config(parent, 0x53 - devno, 0xc3, 1);
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scp->mode[ATA_DEV(device)] = ATA_UDMA4;
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return;
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}
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}
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/* FALLTHROUGH */
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case 0x05961106: /* VIA 82C596 */
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case 0x05861106: /* VIA 82C586 */
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/* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */
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if ((udmamode >= 2 && scp->chiptype == 0x05861106 &&
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pci_read_config(scp->dev, 0x08, 1) >= 0x01) ||
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(udmamode >= 2 && scp->chiptype == 0x05961106) ||
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(udmamode >= 2 && scp->chiptype == 0x74091022)) {
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
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(error) ? "failed" : "success",
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(scp->chiptype == 0x74091022) ? "AMD" : "VIA");
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if (!error) {
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pci_write_config(parent, 0x53 - devno, 0xc0, 1);
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scp->mode[ATA_DEV(device)] = ATA_UDMA2;
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return;
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}
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}
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/* FALLTHROUGH */
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case 0x05711106: /* VIA 82C571 */
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via_generic:
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if (wdmamode >= 2 && apiomode >= 4) {
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
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(error) ? "failed" : "success",
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(scp->chiptype == 0x74091022) ? "AMD" : "VIA");
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if (!error) {
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pci_write_config(parent, 0x53 - devno, 0x82, 1);
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pci_write_config(parent, 0x4b - devno, 0x31, 1);
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scp->mode[ATA_DEV(device)] = ATA_WDMA2;
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return;
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}
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}
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/* we could set PIO mode timings, but we assume the BIOS did that */
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break;
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case 0x55131039: /* SiS 5591 */
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if (udmamode >= 2) {
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device,
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"%s setting up UDMA2 mode on SiS chip\n",
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(error) ? "failed" : "success");
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if (!error) {
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pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
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scp->mode[ATA_DEV(device)] = ATA_UDMA2;
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return;
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}
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}
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if (wdmamode >=2 && apiomode >= 4) {
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device,
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"%s setting up WDMA2 mode on SiS chip\n",
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(error) ? "failed" : "success");
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if (!error) {
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pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
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scp->mode[ATA_DEV(device)] = ATA_WDMA2;
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return;
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}
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}
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/* we could set PIO mode timings, but we assume the BIOS did that */
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break;
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case 0x06461095: /* CMD 646 ATA controller */
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if (wdmamode >= 2 && apiomode >= 4) {
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device,
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"%s setting up WDMA2 mode on CMD646 chip\n",
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error ? "failed" : "success");
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if (!error) {
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int32_t offset = (devno < 3) ? (devno << 1) : 7;
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pci_write_config(parent, 0x54 + offset, 0x3f, 1);
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scp->mode[ATA_DEV(device)] = ATA_WDMA2;
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return;
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}
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}
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/* we could set PIO mode timings, but we assume the BIOS did that */
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break;
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case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */
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case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */
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/* the Promise can only do DMA on ATA disks not on ATAPI devices */
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if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
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(device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
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break;
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if (udmamode >=4 && scp->chiptype == 0x4d38105a &&
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!(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device,
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"%s setting up UDMA4 mode on Promise chip\n",
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(error) ? "failed" : "success");
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if (!error) {
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promise_timing(scp, devno, ATA_UDMA4);
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scp->mode[ATA_DEV(device)] = ATA_UDMA4;
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return;
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}
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}
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if (udmamode >= 2) {
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error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_printf(scp, device,
|
|
"%s setting up UDMA2 mode on Promise chip\n",
|
|
(error) ? "failed" : "success");
|
|
if (!error) {
|
|
promise_timing(scp, devno, ATA_UDMA2);
|
|
scp->mode[ATA_DEV(device)] = ATA_UDMA2;
|
|
return;
|
|
}
|
|
}
|
|
if (wdmamode >= 2 && apiomode >= 4) {
|
|
error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
|
|
ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
|
|
if (bootverbose)
|
|
ata_printf(scp, device,
|
|
"%s setting up WDMA2 mode on Promise chip\n",
|
|
(error) ? "failed" : "success");
|
|
if (!error) {
|
|
promise_timing(scp, devno, ATA_WDMA2);
|
|
scp->mode[ATA_DEV(device)] = ATA_WDMA2;
|
|
return;
|
|
}
|
|
}
|
|
error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
|
|
ata_pio2mode(apiomode),
|
|
ATA_C_F_SETXFER, ATA_WAIT_READY);
|
|
if (bootverbose)
|
|
ata_printf(scp, device,
|
|
"%s setting up PIO%d mode on Promise chip\n",
|
|
(error) ? "failed" : "success",
|
|
(apiomode >= 0) ? apiomode : 0);
|
|
promise_timing(scp, devno, ata_pio2mode(apiomode));
|
|
scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
|
|
return;
|
|
|
|
case 0x00041103: /* HighPoint HPT366 controller */
|
|
/* no ATAPI devices for now */
|
|
if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
|
|
(device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
|
|
break;
|
|
|
|
if (udmamode >=4 && !(pci_read_config(parent, 0x5a, 1) & 0x2)) {
|
|
error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
|
|
ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
|
|
if (bootverbose)
|
|
ata_printf(scp, device,
|
|
"%s setting up UDMA4 mode on HPT366 chip\n",
|
|
(error) ? "failed" : "success");
|
|
if (!error) {
|
|
hpt366_timing(scp, devno, ATA_UDMA4);
|
|
scp->mode[ATA_DEV(device)] = ATA_UDMA4;
|
|
return;
|
|
}
|
|
}
|
|
if (udmamode >= 2) {
|
|
error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
|
|
ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
|
|
if (bootverbose)
|
|
ata_printf(scp, device,
|
|
"%s setting up UDMA2 mode on HPT366 chip\n",
|
|
(error) ? "failed" : "success");
|
|
if (!error) {
|
|
hpt366_timing(scp, devno, ATA_UDMA2);
|
|
scp->mode[ATA_DEV(device)] = ATA_UDMA2;
|
|
return;
|
|
}
|
|
}
|
|
if (wdmamode >= 2 && apiomode >= 4) {
|
|
error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
|
|
ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
|
|
if (bootverbose)
|
|
ata_printf(scp, device,
|
|
"%s setting up WDMA2 mode on HPT366 chip\n",
|
|
(error) ? "failed" : "success");
|
|
if (!error) {
|
|
hpt366_timing(scp, devno, ATA_WDMA2);
|
|
scp->mode[ATA_DEV(device)] = ATA_WDMA2;
|
|
return;
|
|
}
|
|
}
|
|
error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
|
|
ata_pio2mode(apiomode),
|
|
ATA_C_F_SETXFER, ATA_WAIT_READY);
|
|
if (bootverbose)
|
|
ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n",
|
|
(error) ? "failed" : "success",
|
|
(apiomode >= 0) ? apiomode : 0);
|
|
hpt366_timing(scp, devno, ata_pio2mode(apiomode));
|
|
scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
|
|
return;
|
|
|
|
default: /* unknown controller chip */
|
|
/* better not try generic DMA on ATAPI devices it almost never works */
|
|
if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
|
|
(device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
|
|
break;
|
|
|
|
/* if controller says its setup for DMA take the easy way out */
|
|
/* the downside is we dont know what DMA mode we are in */
|
|
if ((udmamode >= 0 || wdmamode > 1) &&
|
|
(inb(scp->bmaddr + ATA_BMSTAT_PORT) &
|
|
((device==ATA_MASTER) ?
|
|
ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
|
|
scp->mode[ATA_DEV(device)] = ATA_DMA;
|
|
return;
|
|
}
|
|
|
|
/* well, we have no support for this, but try anyways */
|
|
if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) {
|
|
error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
|
|
ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
|
|
if (bootverbose)
|
|
ata_printf(scp, device,
|
|
"%s setting up WDMA2 mode on generic chip\n",
|
|
(error) ? "failed" : "success");
|
|
if (!error) {
|
|
scp->mode[ATA_DEV(device)] = ATA_WDMA2;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
|
|
ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY);
|
|
if (bootverbose)
|
|
ata_printf(scp, device, "%s setting up PIO%d mode on generic chip\n",
|
|
(error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
|
|
if (!error)
|
|
scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
|
|
else
|
|
if (bootverbose)
|
|
ata_printf(scp, device, "using PIO mode set by BIOS\n");
|
|
}
|
|
|
|
int32_t
|
|
ata_dmasetup(struct ata_softc *scp, int32_t device,
|
|
int8_t *data, int32_t count, int32_t flags)
|
|
{
|
|
struct ata_dmaentry *dmatab;
|
|
u_int32_t dma_count, dma_base;
|
|
int32_t i = 0;
|
|
|
|
if (((uintptr_t)data & 1) || (count & 1))
|
|
return -1;
|
|
|
|
if (!count) {
|
|
ata_printf(scp, device, "zero length DMA transfer attempted\n");
|
|
return -1;
|
|
}
|
|
|
|
dmatab = scp->dmatab[ATA_DEV(device)];
|
|
dma_base = vtophys(data);
|
|
dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
|
|
data += dma_count;
|
|
count -= dma_count;
|
|
|
|
while (count) {
|
|
dmatab[i].base = dma_base;
|
|
dmatab[i].count = (dma_count & 0xffff);
|
|
i++;
|
|
if (i >= ATA_DMA_ENTRIES) {
|
|
ata_printf(scp, device, "too many segments in DMA table\n");
|
|
return -1;
|
|
}
|
|
dma_base = vtophys(data);
|
|
dma_count = min(count, PAGE_SIZE);
|
|
data += min(count, PAGE_SIZE);
|
|
count -= min(count, PAGE_SIZE);
|
|
}
|
|
dmatab[i].base = dma_base;
|
|
dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
|
|
outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab));
|
|
outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0);
|
|
outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) |
|
|
(ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
ata_dmastart(struct ata_softc *scp)
|
|
{
|
|
scp->flags |= ATA_DMA_ACTIVE;
|
|
outb(scp->bmaddr + ATA_BMCMD_PORT,
|
|
inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
|
|
}
|
|
|
|
int32_t
|
|
ata_dmadone(struct ata_softc *scp)
|
|
{
|
|
outb(scp->bmaddr + ATA_BMCMD_PORT,
|
|
inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
|
|
scp->flags &= ~ATA_DMA_ACTIVE;
|
|
return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
|
|
}
|
|
|
|
int32_t
|
|
ata_dmastatus(struct ata_softc *scp)
|
|
{
|
|
return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
|
|
}
|
|
|
|
static void
|
|
promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
|
|
{
|
|
u_int32_t timing = 0;
|
|
struct promise_timing {
|
|
u_int8_t pa:4;
|
|
u_int8_t prefetch:1;
|
|
u_int8_t iordy:1;
|
|
u_int8_t errdy:1;
|
|
u_int8_t syncin:1;
|
|
u_int8_t pb:5;
|
|
u_int8_t mb:3;
|
|
u_int8_t mc:4;
|
|
u_int8_t dmaw:1;
|
|
u_int8_t dmar:1;
|
|
u_int8_t iordyp:1;
|
|
u_int8_t dmarqp:1;
|
|
u_int8_t reserved:8;
|
|
} *t = (struct promise_timing*)&timing;
|
|
|
|
t->iordy = 1; t->iordyp = 1;
|
|
if (mode >= ATA_DMA) {
|
|
t->prefetch = 1; t->errdy = 1; t->syncin = 1;
|
|
}
|
|
|
|
switch (scp->chiptype) {
|
|
case 0x4d33105a: /* Promise 33's */
|
|
switch (mode) {
|
|
default:
|
|
case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
|
|
case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
|
|
case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
|
|
case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
|
|
case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
|
|
case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
|
|
case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
|
|
}
|
|
break;
|
|
|
|
case 0x4d38105a: /* Promise 66's */
|
|
switch (mode) {
|
|
default:
|
|
case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
|
|
case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
|
|
case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
|
|
case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
|
|
case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
|
|
case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
|
|
case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
|
|
case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
|
|
}
|
|
break;
|
|
}
|
|
pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
|
|
}
|
|
|
|
static void
|
|
hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
|
|
{
|
|
device_t parent = device_get_parent(scp->dev);
|
|
u_int32_t timing;
|
|
|
|
switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
|
|
case 0x85: /* 25Mhz */
|
|
switch (mode) {
|
|
case ATA_PIO0: timing = 0xc0d08585; break;
|
|
case ATA_PIO1: timing = 0xc0d08572; break;
|
|
case ATA_PIO2: timing = 0xc0ca8542; break;
|
|
case ATA_PIO3: timing = 0xc0ca8532; break;
|
|
case ATA_PIO4: timing = 0xc0ca8521; break;
|
|
case ATA_WDMA2: timing = 0xa0ca8521; break;
|
|
case ATA_UDMA2: timing = 0x90cf8521; break;
|
|
case ATA_UDMA4: timing = 0x90c98521; break;
|
|
default: timing = 0x01208585;
|
|
}
|
|
break;
|
|
default:
|
|
case 0xa7: /* 33MHz */
|
|
switch (mode) {
|
|
case ATA_PIO0: timing = 0xc0d0a7aa; break;
|
|
case ATA_PIO1: timing = 0xc0d0a7a3; break;
|
|
case ATA_PIO2: timing = 0xc0d0a753; break;
|
|
case ATA_PIO3: timing = 0xc0c8a742; break;
|
|
case ATA_PIO4: timing = 0xc0c8a731; break;
|
|
case ATA_WDMA2: timing = 0xa0c8a731; break;
|
|
case ATA_UDMA2: timing = 0x90caa731; break;
|
|
case ATA_UDMA4: timing = 0x90c9a731; break;
|
|
default: timing = 0x0120a7a7;
|
|
}
|
|
break;
|
|
case 0xd9: /* 40Mhz */
|
|
switch (mode) {
|
|
case ATA_PIO0: timing = 0xc018d9d9; break;
|
|
case ATA_PIO1: timing = 0xc010d9c7; break;
|
|
case ATA_PIO2: timing = 0xc010d997; break;
|
|
case ATA_PIO3: timing = 0xc010d974; break;
|
|
case ATA_PIO4: timing = 0xc008d963; break;
|
|
case ATA_WDMA2: timing = 0xa008d943; break;
|
|
case ATA_UDMA2: timing = 0x900bd943; break;
|
|
case ATA_UDMA4: timing = 0x900fd943; break;
|
|
default: timing = 0x0120d9d9;
|
|
}
|
|
}
|
|
pci_write_config(parent, 0x40 + (devno << 2) , (timing & ~0x80000000), 4);
|
|
}
|
|
|
|
#else /* NPCI > 0 */
|
|
|
|
void
|
|
ata_dmainit(struct ata_softc *scp, int32_t device,
|
|
int32_t piomode, int32_t wdmamode, int32_t udmamode)
|
|
{
|
|
}
|
|
|
|
int32_t
|
|
ata_dmasetup(struct ata_softc *scp, int32_t device,
|
|
int8_t *data, int32_t count, int32_t flags)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
void
|
|
ata_dmastart(struct ata_softc *scp)
|
|
{
|
|
}
|
|
|
|
int32_t
|
|
ata_dmadone(struct ata_softc *scp)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
int32_t
|
|
ata_dmastatus(struct ata_softc *scp)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
#endif /* NPCI > 0 */
|