1114 lines
22 KiB
Reg
1114 lines
22 KiB
Reg
/*
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* Aic7xxx register and scratch ram definitions.
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*
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* Copyright (c) 1994, 1995, 1996, 1997 Justin T. Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: aic7xxx.reg,v 1.1 1997/03/16 07:08:11 gibbs Exp $
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*/
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/*
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* This file is processed by the aic7xxx_asm utility for use in assembling
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* firmware for the aic7xxx family of SCSI host adapters as well as to generate
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* a C header file for use in the kernel portion of the Aic7xxx driver.
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*
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* All page numbers refer to the Adaptec AIC-7770 Data Book available from
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* Adaptec's Technical Documents Department 1-800-934-2766
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*/
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/*
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* SCSI Sequence Control (p. 3-11).
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* Each bit, when set starts a specific SCSI sequence on the bus
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*/
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register SCSISEQ {
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address 0x000
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access_mode RW
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bit TEMODE 0x80
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bit ENSELO 0x40
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bit ENSELI 0x20
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bit ENRSELI 0x10
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bit ENAUTOATNO 0x08
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bit ENAUTOATNI 0x04
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bit ENAUTOATNP 0x02
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bit SCSIRSTO 0x01
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}
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/*
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* SCSI Transfer Control 0 Register (pp. 3-13).
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* Controls the SCSI module data path.
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*/
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register SXFRCTL0 {
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address 0x001
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access_mode RW
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bit DFON 0x80
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bit DFPEXP 0x40
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bit FAST20 0x20
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bit CLRSTCNT 0x10
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bit SPIOEN 0x08
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bit SCAMEN 0x04
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bit CLRCHN 0x02
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}
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/*
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* SCSI Transfer Control 1 Register (pp. 3-14,15).
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* Controls the SCSI module data path.
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*/
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register SXFRCTL1 {
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address 0x002
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access_mode RW
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bit BITBUCKET 0x80
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bit SWRAPEN 0x40
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bit ENSPCHK 0x20
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mask STIMESEL 0x18
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bit ENSTIMER 0x04
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bit ACTNEGEN 0x02
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bit STPWEN 0x01 /* Powered Termination */
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}
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/*
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* SCSI Control Signal Read Register (p. 3-15).
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* Reads the actual state of the SCSI bus pins
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*/
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register SCSISIGI {
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address 0x003
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access_mode RO
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bit CDI 0x80
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bit IOI 0x40
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bit MSGI 0x20
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bit ATNI 0x10
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bit SELI 0x08
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bit BSYI 0x04
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bit REQI 0x02
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bit ACKI 0x01
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/*
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* Possible phases in SCSISIGI
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*/
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mask PHASE_MASK CDI|IOI|MSGI
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mask P_DATAOUT 0x00
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mask P_DATAIN IOI
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mask P_COMMAND CDI
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mask P_MESGOUT CDI|MSGI
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mask P_STATUS CDI|IOI
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mask P_MESGIN CDI|IOI|MSGI
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}
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/*
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* SCSI Control Signal Write Register (p. 3-16).
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* Writing to this register modifies the control signals on the bus. Only
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* those signals that are allowed in the current mode (Initiator/Target) are
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* asserted.
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*/
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register SCSISIGO {
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address 0x003
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access_mode WO
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bit CDO 0x80
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bit IOO 0x40
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bit MSGO 0x20
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bit ATNO 0x10
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bit SELO 0x08
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bit BSYO 0x04
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bit REQO 0x02
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bit ACKO 0x01
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/*
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* Possible phases to write into SCSISIG0
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*/
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mask PHASE_MASK CDI|IOI|MSGI
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mask P_DATAOUT 0x00
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mask P_DATAIN IOI
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mask P_COMMAND CDI
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mask P_MESGOUT CDI|MSGI
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mask P_STATUS CDI|IOI
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mask P_MESGIN CDI|IOI|MSGI
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}
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/*
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* SCSI Rate Control (p. 3-17).
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* Contents of this register determine the Synchronous SCSI data transfer
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* rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
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* SOFS (3:0) bits disables synchronous data transfers. Any offset value
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* greater than 0 enables synchronous transfers.
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*/
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register SCSIRATE {
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address 0x004
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access_mode RW
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bit WIDEXFER 0x80 /* Wide transfer control */
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mask SXFR 0x70 /* Sync transfer rate */
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mask SOFS 0x0f /* Sync offset */
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}
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/*
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* SCSI ID (p. 3-18).
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* Contains the ID of the board and the current target on the
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* selected channel.
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*/
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register SCSIID {
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address 0x005
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access_mode RW
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mask TID 0xf0 /* Target ID mask */
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mask OID 0x0f /* Our ID mask */
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}
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/*
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* SCSI Latched Data (p. 3-19).
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* Read/Write latches used to transfer data on the SCSI bus during
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* Automatic or Manual PIO mode. SCSIDATH can be used for the
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* upper byte of a 16bit wide asynchronouse data phase transfer.
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*/
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register SCSIDATL {
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address 0x006
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access_mode RW
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}
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register SCSIDATH {
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address 0x007
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access_mode RW
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}
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/*
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* SCSI Transfer Count (pp. 3-19,20)
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* These registers count down the number of bytes transferred
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* across the SCSI bus. The counter is decremented only once
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* the data has been safely transferred. SDONE in SSTAT0 is
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* set when STCNT goes to 0
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*/
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register STCNT {
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address 0x008
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size 3
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access_mode RW
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}
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/*
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* Clear SCSI Interrupt 0 (p. 3-20)
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* Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
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*/
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register CLRSINT0 {
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address 0x00b
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access_mode WO
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bit CLRSELDO 0x40
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bit CLRSELDI 0x20
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bit CLRSELINGO 0x10
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bit CLRSWRAP 0x08
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bit CLRSPIORDY 0x02
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}
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/*
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* SCSI Status 0 (p. 3-21)
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* Contains one set of SCSI Interrupt codes
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* These are most likely of interest to the sequencer
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*/
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register SSTAT0 {
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address 0x00b
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access_mode RO
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bit TARGET 0x80 /* Board acting as target */
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bit SELDO 0x40 /* Selection Done */
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bit SELDI 0x20 /* Board has been selected */
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bit SELINGO 0x10 /* Selection In Progress */
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bit SWRAP 0x08 /* 24bit counter wrap */
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bit SDONE 0x04 /* STCNT = 0x000000 */
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bit SPIORDY 0x02 /* SCSI PIO Ready */
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bit DMADONE 0x01 /* DMA transfer completed */
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}
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/*
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* Clear SCSI Interrupt 1 (p. 3-23)
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* Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
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*/
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register CLRSINT1 {
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address 0x00c
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access_mode WO
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bit CLRSELTIMEO 0x80
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bit CLRATNO 0x40
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bit CLRSCSIRSTI 0x20
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bit CLRBUSFREE 0x08
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bit CLRSCSIPERR 0x04
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bit CLRPHASECHG 0x02
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bit CLRREQINIT 0x01
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}
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/*
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* SCSI Status 1 (p. 3-24)
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*/
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register SSTAT1 {
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address 0x00c
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access_mode RO
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bit SELTO 0x80
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bit ATNTARG 0x40
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bit SCSIRSTI 0x20
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bit PHASEMIS 0x10
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bit BUSFREE 0x08
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bit SCSIPERR 0x04
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bit PHASECHG 0x02
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bit REQINIT 0x01
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}
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/*
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* SCSI Status 2 (pp. 3-25,26)
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*/
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register SSTAT2 {
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address 0x00d
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access_mode RO
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bit OVERRUN 0x80
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mask SFCNT 0x1f
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}
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/*
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* SCSI Status 3 (p. 3-26)
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*/
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register SSTAT3 {
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address 0x00e
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access_mode RO
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mask SCSICNT 0xf0
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mask OFFCNT 0x0f
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}
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/*
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* SCSI Test Control (p. 3-27)
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*/
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register SCSITEST {
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address 0x00f
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access_mode RW
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bit RQAKCNT 0x04
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bit CNTRTEST 0x02
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bit CMODE 0x01
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}
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/*
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* SCSI Interrupt Mode 1 (p. 3-28)
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* Setting any bit will enable the corresponding function
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* in SIMODE0 to interrupt via the IRQ pin.
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*/
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register SIMODE0 {
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address 0x010
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access_mode RW
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bit ENSELDO 0x40
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bit ENSELDI 0x20
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bit ENSELINGO 0x10
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bit ENSWRAP 0x08
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bit ENSDONE 0x04
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bit ENSPIORDY 0x02
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bit ENDMADONE 0x01
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}
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/*
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* SCSI Interrupt Mode 1 (pp. 3-28,29)
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* Setting any bit will enable the corresponding function
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* in SIMODE1 to interrupt via the IRQ pin.
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*/
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register SIMODE1 {
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address 0x011
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access_mode RW
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bit ENSELTIMO 0x80
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bit ENATNTARG 0x40
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bit ENSCSIRST 0x20
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bit ENPHASEMIS 0x10
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bit ENBUSFREE 0x08
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bit ENSCSIPERR 0x04
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bit ENPHASECHG 0x02
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bit ENREQINIT 0x01
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}
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/*
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* SCSI Data Bus (High) (p. 3-29)
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* This register reads data on the SCSI Data bus directly.
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*/
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register SCSIBUSL {
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address 0x012
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access_mode RO
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}
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register SCSIBUSH {
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address 0x013
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access_mode RO
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}
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/*
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* SCSI/Host Address (p. 3-30)
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* These registers hold the host address for the byte about to be
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* transferred on the SCSI bus. They are counted up in the same
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* manner as STCNT is counted down. SHADDR should always be used
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* to determine the address of the last byte transferred since HADDR
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* can be skewed by write ahead.
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*/
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register SHADDR {
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address 0x014
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size 4
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access_mode RO
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}
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/*
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* Selection Timeout Timer (p. 3-30)
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*/
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register SELTIMER {
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address 0x018
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access_mode RW
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bit STAGE6 0x20
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bit STAGE5 0x10
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bit STAGE4 0x08
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bit STAGE3 0x04
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bit STAGE2 0x02
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bit STAGE1 0x01
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}
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/*
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* Selection/Reselection ID (p. 3-31)
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* Upper four bits are the device id. The ONEBIT is set when the re/selecting
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* device did not set its own ID.
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*/
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register SELID {
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address 0x019
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access_mode RW
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mask SELID_MASK 0xf0
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bit ONEBIT 0x08
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}
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/*
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* SCSI Block Control (p. 3-32)
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* Controls Bus type and channel selection. In a twin channel configuration
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* addresses 0x00-0x1e are gated to the appropriate channel based on this
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* register. SELWIDE allows for the coexistence of 8bit and 16bit devices
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* on a wide bus.
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*/
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register SBLKCTL {
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address 0x01f
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access_mode RW
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bit DIAGLEDEN 0x80 /* Aic78X0 only */
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bit DIAGLEDON 0x40 /* Aic78X0 only */
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bit AUTOFLUSHDIS 0x20
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bit SELBUSB 0x08
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bit SELWIDE 0x02
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}
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/*
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* Sequencer Control (p. 3-33)
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* Error detection mode and speed configuration
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*/
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register SEQCTL {
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address 0x060
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access_mode RW
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bit PERRORDIS 0x80
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bit PAUSEDIS 0x40
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bit FAILDIS 0x20
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bit FASTMODE 0x10
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bit BRKADRINTEN 0x08
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bit STEP 0x04
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bit SEQRESET 0x02
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bit LOADRAM 0x01
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}
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/*
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* Sequencer RAM Data (p. 3-34)
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* Single byte window into the Scratch Ram area starting at the address
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* specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
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* four bytes in sucessesion. The SEQADDRs will increment after the most
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* significant byte is written
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*/
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register SEQRAM {
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address 0x061
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access_mode RW
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}
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/*
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* Sequencer Address Registers (p. 3-35)
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* Only the first bit of SEQADDR1 holds addressing information
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*/
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register SEQADDR0 {
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address 0x062
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access_mode RW
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}
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register SEQADDR1 {
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address 0x063
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access_mode RW
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mask SEQADDR1_MASK 0x01
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}
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/*
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* Accumulator
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* We cheat by passing arguments in the Accumulator up to the kernel driver
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*/
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register ACCUM {
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address 0x064
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access_mode RW
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accumulator
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}
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register SINDEX {
|
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address 0x065
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access_mode RW
|
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sindex
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|
}
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|
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|
register DINDEX {
|
|
address 0x066
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access_mode RW
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}
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register ALLONES {
|
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address 0x069
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access_mode RO
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allones
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}
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|
register ALLZEROS {
|
|
address 0x06a
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access_mode RO
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allzeros
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}
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register NONE {
|
|
address 0x06a
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access_mode WO
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none
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}
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|
|
register FLAGS {
|
|
address 0x06b
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|
access_mode RO
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bit ZERO 0x02
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bit CARRY 0x01
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}
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|
register SINDIR {
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address 0x06c
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|
access_mode RO
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}
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|
|
|
register DINDIR {
|
|
address 0x06d
|
|
access_mode WO
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|
}
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|
|
|
register FUNCTION1 {
|
|
address 0x06e
|
|
access_mode RW
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|
}
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|
|
|
register STACK {
|
|
address 0x06f
|
|
access_mode RO
|
|
}
|
|
|
|
/*
|
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* Board Control (p. 3-43)
|
|
*/
|
|
register BCTL {
|
|
address 0x084
|
|
access_mode RW
|
|
bit ACE 0x08
|
|
bit ENABLE 0x01
|
|
}
|
|
|
|
/*
|
|
* On the aic78X0 chips, Board Control is replaced by the DSCommand
|
|
* register (p. 4-64)
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|
*/
|
|
register DSCOMMAND {
|
|
address 0x084
|
|
access_mode RW
|
|
bit CACHETHEN 0x80 /* Cache Threshold enable */
|
|
bit DPARCKEN 0x40 /* Data Parity Check Enable */
|
|
bit MPARCKEN 0x20 /* Memory Parity Check Enable */
|
|
bit EXTREQLCK 0x10 /* External Request Lock */
|
|
}
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|
|
|
/*
|
|
* Bus On/Off Time (p. 3-44)
|
|
*/
|
|
register BUSTIME {
|
|
address 0x085
|
|
access_mode RW
|
|
mask BOFF 0xf0
|
|
mask BON 0x0f
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|
}
|
|
|
|
/*
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|
* Bus Speed (p. 3-45)
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*/
|
|
register BUSSPD {
|
|
address 0x086
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|
access_mode RW
|
|
mask DFTHRSH 0xc0
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|
mask STBOFF 0x38
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|
mask STBON 0x07
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|
mask DFTHRSH_100 0xc0
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|
}
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|
|
|
/*
|
|
* Host Control (p. 3-47) R/W
|
|
* Overall host control of the device.
|
|
*/
|
|
register HCNTRL {
|
|
address 0x087
|
|
access_mode RW
|
|
bit POWRDN 0x40
|
|
bit SWINT 0x10
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|
bit IRQMS 0x08
|
|
bit PAUSE 0x04
|
|
bit INTEN 0x02
|
|
bit CHIPRST 0x01
|
|
bit CHIPRSTACK 0x01
|
|
}
|
|
|
|
/*
|
|
* Host Address (p. 3-48)
|
|
* This register contains the address of the byte about
|
|
* to be transferred across the host bus.
|
|
*/
|
|
register HADDR {
|
|
address 0x088
|
|
size 4
|
|
access_mode RW
|
|
}
|
|
|
|
register HCNT {
|
|
address 0x08c
|
|
size 3
|
|
access_mode RW
|
|
}
|
|
|
|
/*
|
|
* SCB Pointer (p. 3-49)
|
|
* Gate one of the four SCBs into the SCBARRAY window.
|
|
*/
|
|
register SCBPTR {
|
|
address 0x090
|
|
access_mode RW
|
|
}
|
|
|
|
/*
|
|
* Interrupt Status (p. 3-50)
|
|
* Status for system interrupts
|
|
*/
|
|
register INTSTAT {
|
|
address 0x091
|
|
access_mode RW
|
|
bit BRKADRINT 0x08
|
|
bit SCSIINT 0x04
|
|
bit CMDCMPLT 0x02
|
|
bit SEQINT 0x01
|
|
mask BAD_PHASE SEQINT /* unknown scsi bus phase */
|
|
mask SEND_REJECT 0x10|SEQINT /* sending a message reject */
|
|
mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/
|
|
mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */
|
|
mask EXTENDED_MSG 0x40|SEQINT /* Extended message received */
|
|
mask NO_MATCH_BUSY 0x50|SEQINT /* Couldn't find BUSY SCB */
|
|
mask REJECT_MSG 0x60|SEQINT /* Reject message received */
|
|
mask BAD_STATUS 0x70|SEQINT /* Bad status from target */
|
|
mask RESIDUAL 0x80|SEQINT /* Residual byte count != 0 */
|
|
mask ABORT_CMDCMPLT 0x91 /*
|
|
* Command tagged for abort
|
|
* completed successfully.
|
|
*/
|
|
mask AWAITING_MSG 0xa0|SEQINT /*
|
|
* Kernel requested to specify
|
|
* a message to this target
|
|
* (command was null), so tell
|
|
* it that it can fill the
|
|
* message buffer.
|
|
*/
|
|
mask MSG_BUFFER_BUSY 0xc0|SEQINT /*
|
|
* Sequencer wants to use the
|
|
* message buffer, but it
|
|
* already contains a message
|
|
*/
|
|
mask MSGIN_PHASEMIS 0xd0|SEQINT /*
|
|
* Target changed phase on us
|
|
* when we were expecting
|
|
* another msgin byte.
|
|
*/
|
|
mask DATA_OVERRUN 0xe0|SEQINT /*
|
|
* Target attempted to write
|
|
* beyond the bounds of its
|
|
* command.
|
|
*/
|
|
|
|
mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */
|
|
mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
|
|
}
|
|
|
|
/*
|
|
* Hard Error (p. 3-53)
|
|
* Reporting of catastrophic errors. You usually cannot recover from
|
|
* these without a full board reset.
|
|
*/
|
|
register ERROR {
|
|
address 0x092
|
|
access_mode RO
|
|
bit PARERR 0x08
|
|
bit ILLOPCODE 0x04
|
|
bit ILLSADDR 0x02
|
|
bit ILLHADDR 0x01
|
|
}
|
|
|
|
/*
|
|
* Clear Interrupt Status (p. 3-52)
|
|
*/
|
|
register CLRINT {
|
|
address 0x092
|
|
access_mode WO
|
|
bit CLRBRKADRINT 0x08
|
|
bit CLRSCSIINT 0x04
|
|
bit CLRCMDINT 0x02
|
|
bit CLRSEQINT 0x01
|
|
}
|
|
|
|
register DFCNTRL {
|
|
address 0x093
|
|
access_mode RW
|
|
bit WIDEODD 0x40
|
|
bit SCSIEN 0x20
|
|
bit SDMAEN 0x10
|
|
bit SDMAENACK 0x10
|
|
bit HDMAEN 0x08
|
|
bit HDMAENACK 0x08
|
|
bit DIRECTION 0x04
|
|
bit FIFOFLUSH 0x02
|
|
bit FIFORESET 0x01
|
|
}
|
|
|
|
register DFSTATUS {
|
|
address 0x094
|
|
access_mode RO
|
|
bit DWORDEMP 0x20
|
|
bit MREQPEND 0x10
|
|
bit HDONE 0x08
|
|
bit DFTHRESH 0x04
|
|
bit FIFOFULL 0x02
|
|
bit FIFOEMP 0x01
|
|
}
|
|
|
|
register DFDAT {
|
|
address 0x099
|
|
access_mode RW
|
|
}
|
|
|
|
/*
|
|
* SCB Auto Increment (p. 3-59)
|
|
* Byte offset into the SCB Array and an optional bit to allow auto
|
|
* incrementing of the address during download and upload operations
|
|
*/
|
|
register SCBCNT {
|
|
address 0x09a
|
|
access_mode RW
|
|
bit SCBAUTO 0x80
|
|
mask SCBCNT_MASK 0x1f
|
|
}
|
|
|
|
/*
|
|
* Queue In FIFO (p. 3-60)
|
|
* Input queue for queued SCBs (commands that the seqencer has yet to start)
|
|
*/
|
|
register QINFIFO {
|
|
address 0x09b
|
|
access_mode RW
|
|
}
|
|
|
|
/*
|
|
* Queue In Count (p. 3-60)
|
|
* Number of queued SCBs
|
|
*/
|
|
register QINCNT {
|
|
address 0x09c
|
|
access_mode RO
|
|
}
|
|
|
|
/*
|
|
* Queue Out FIFO (p. 3-61)
|
|
* Queue of SCBs that have completed and await the host
|
|
*/
|
|
register QOUTFIFO {
|
|
address 0x09d
|
|
access_mode WO
|
|
}
|
|
|
|
/*
|
|
* Queue Out Count (p. 3-61)
|
|
* Number of queued SCBs in the Out FIFO
|
|
*/
|
|
register QOUTCNT {
|
|
address 0x09e
|
|
access_mode RO
|
|
}
|
|
|
|
/*
|
|
* SCB Definition (p. 5-4)
|
|
*/
|
|
scb {
|
|
address 0x0a0
|
|
SCB_CONTROL {
|
|
size 1
|
|
bit MK_MESSAGE 0x80
|
|
bit DISCENB 0x40
|
|
bit TAG_ENB 0x20
|
|
bit SPLIT_SG 0x10
|
|
bit ABORT_SCB 0x08
|
|
bit DISCONNECTED 0x04
|
|
mask SCB_TAG_TYPE 0x03
|
|
}
|
|
SCB_TCL {
|
|
size 1
|
|
bit SELBUSB 0x08
|
|
mask TID 0xf0
|
|
mask LID 0x07
|
|
}
|
|
SCB_TARGET_STATUS {
|
|
size 1
|
|
}
|
|
SCB_SGCOUNT {
|
|
size 1
|
|
}
|
|
SCB_SGPTR {
|
|
size 4
|
|
}
|
|
SCB_RESID_SGCNT {
|
|
size 1
|
|
}
|
|
SCB_RESID_DCNT {
|
|
size 3
|
|
}
|
|
SCB_DATAPTR {
|
|
size 4
|
|
}
|
|
SCB_DATACNT {
|
|
size 3
|
|
}
|
|
SCB_LINKED_NEXT {
|
|
size 1
|
|
}
|
|
SCB_CMDPTR {
|
|
size 4
|
|
}
|
|
SCB_CMDLEN {
|
|
size 1
|
|
}
|
|
SCB_TAG {
|
|
size 1
|
|
}
|
|
SCB_NEXT {
|
|
size 1
|
|
}
|
|
SCB_PREV {
|
|
size 1
|
|
}
|
|
SCB_BUSYTARGETS {
|
|
size 4
|
|
}
|
|
}
|
|
|
|
const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */
|
|
|
|
/* --------------------- AHA-2840-only definitions -------------------- */
|
|
|
|
register SEECTL_2840 {
|
|
address 0x0c0
|
|
access_mode RW
|
|
bit CS_2840 0x04
|
|
bit CK_2840 0x02
|
|
bit DO_2840 0x01
|
|
}
|
|
|
|
register STATUS_2840 {
|
|
address 0x0c1
|
|
access_mode RW
|
|
bit EEPROM_TF 0x80
|
|
mask BIOS_SEL 0x60
|
|
mask ADSEL 0x1e
|
|
bit DI_2840 0x01
|
|
}
|
|
|
|
/* --------------------- AIC-7870-only definitions -------------------- */
|
|
|
|
register DSPCISTATUS {
|
|
address 0x086
|
|
}
|
|
|
|
register BRDCTL {
|
|
address 0x01d
|
|
bit BRDDAT7 0x80
|
|
bit BRDDAT6 0x40
|
|
bit BRDDAT5 0x20
|
|
bit BRDSTB 0x10
|
|
bit BRDCS 0x08
|
|
bit BRDRW 0x04
|
|
bit BRDCTL1 0x02
|
|
bit BRDCTL0 0x01
|
|
}
|
|
|
|
/*
|
|
* Serial EEPROM Control (p. 4-92 in 7870 Databook)
|
|
* Controls the reading and writing of an external serial 1-bit
|
|
* EEPROM Device. In order to access the serial EEPROM, you must
|
|
* first set the SEEMS bit that generates a request to the memory
|
|
* port for access to the serial EEPROM device. When the memory
|
|
* port is not busy servicing another request, it reconfigures
|
|
* to allow access to the serial EEPROM. When this happens, SEERDY
|
|
* gets set high to verify that the memory port access has been
|
|
* granted.
|
|
*
|
|
* After successful arbitration for the memory port, the SEECS bit of
|
|
* the SEECTL register is connected to the chip select. The SEECK,
|
|
* SEEDO, and SEEDI are connected to the clock, data out, and data in
|
|
* lines respectively. The SEERDY bit of SEECTL is useful in that it
|
|
* gives us an 800 nsec timer. After a write to the SEECTL register,
|
|
* the SEERDY goes high 800 nsec later. The one exception to this is
|
|
* when we first request access to the memory port. The SEERDY goes
|
|
* high to signify that access has been granted and, for this case, has
|
|
* no implied timing.
|
|
*
|
|
* See 93cx6.c for detailed information on the protocol necessary to
|
|
* read the serial EEPROM.
|
|
*/
|
|
register SEECTL {
|
|
address 0x01e
|
|
bit EXTARBACK 0x80
|
|
bit EXTARBREQ 0x40
|
|
bit SEEMS 0x20
|
|
bit SEERDY 0x10
|
|
bit SEECS 0x08
|
|
bit SEECK 0x04
|
|
bit SEEDO 0x02
|
|
bit SEEDI 0x01
|
|
}
|
|
/* ---------------------- Scratch RAM Offsets ------------------------- */
|
|
/* These offsets are either to values that are initialized by the board's
|
|
* BIOS or are specified by the sequencer code.
|
|
*
|
|
* The host adapter card (at least the BIOS) uses 20-2f for SCSI
|
|
* device information, 32-33 and 5a-5f as well. As it turns out, the
|
|
* BIOS trashes 20-2f, writing the synchronous negotiation results
|
|
* on top of the BIOS values, so we re-use those for our per-target
|
|
* scratchspace (actually a value that can be copied directly into
|
|
* SCSIRATE). The kernel driver will enable synchronous negotiation
|
|
* for all targets that have a value other than 0 in the lower four
|
|
* bits of the target scratch space. This should work regardless of
|
|
* whether the bios has been installed.
|
|
*/
|
|
|
|
scratch_ram {
|
|
address 0x020
|
|
|
|
/*
|
|
* 1 byte per target starting at this address for configuration values
|
|
*/
|
|
TARG_SCRATCH {
|
|
size 16
|
|
}
|
|
ULTRA_ENB {
|
|
size 2
|
|
}
|
|
/*
|
|
* Bit vector of targets that have disconnection disabled.
|
|
*/
|
|
DISC_DSB {
|
|
size 2
|
|
}
|
|
/*
|
|
* Length of pending message
|
|
*/
|
|
MSG_LEN {
|
|
size 1
|
|
}
|
|
/* We reserve 8bytes to store outgoing messages */
|
|
MSG_OUT {
|
|
size 8
|
|
}
|
|
/* Parameters for DMA Logic */
|
|
DMAPARAMS {
|
|
size 1
|
|
bit WIDEODD 0x40
|
|
bit SCSIEN 0x20
|
|
bit SDMAEN 0x10
|
|
bit SDMAENACK 0x10
|
|
bit HDMAEN 0x08
|
|
bit HDMAENACK 0x08
|
|
bit DIRECTION 0x04
|
|
bit FIFOFLUSH 0x02
|
|
bit FIFORESET 0x01
|
|
}
|
|
/*
|
|
* Number of SCBs supported by
|
|
* this card.
|
|
*/
|
|
SCBCOUNT {
|
|
size 1
|
|
}
|
|
/*
|
|
* Two's complement of SCBCOUNT
|
|
*/
|
|
COMP_SCBCOUNT {
|
|
size 1
|
|
}
|
|
/*
|
|
* Mask of bits to test against
|
|
* when looking at the Queue Count
|
|
* registers. Works around a bug
|
|
* on aic7850 chips.
|
|
*/
|
|
QCNTMASK {
|
|
size 1
|
|
}
|
|
SEQ_FLAGS {
|
|
size 1
|
|
bit RESELECTED 0x80
|
|
bit IDENTIFY_SEEN 0x40
|
|
bit TAGGED_SCB 0x20
|
|
bit DPHASE 0x10
|
|
bit PAGESCBS 0x04
|
|
bit WIDE_BUS 0x02
|
|
bit TWIN_BUS 0x01
|
|
}
|
|
/*
|
|
* Temporary storage for the
|
|
* target/channel/lun of a
|
|
* reconnecting target
|
|
*/
|
|
SAVED_TCL {
|
|
size 1
|
|
}
|
|
SG_COUNT {
|
|
size 1
|
|
}
|
|
/* working value of SG pointer */
|
|
SG_NEXT {
|
|
size 4
|
|
}
|
|
/*
|
|
* head of list of SCBs awaiting
|
|
* selection
|
|
*/
|
|
WAITING_SCBH {
|
|
size 1
|
|
}
|
|
SAVED_LINKPTR {
|
|
size 1
|
|
}
|
|
SAVED_SCBPTR {
|
|
size 1
|
|
}
|
|
/*
|
|
* The sequencer will stick the frist byte of any rejected message here
|
|
* so we can see what is getting thrown away.
|
|
*/
|
|
REJBYTE {
|
|
size 1
|
|
}
|
|
/*
|
|
* The last bus phase as seen by the sequencer.
|
|
*/
|
|
LASTPHASE {
|
|
size 1
|
|
bit CDI 0x80
|
|
bit IOI 0x40
|
|
bit MSGI 0x20
|
|
mask PHASE_MASK CDI|IOI|MSGI
|
|
mask P_DATAOUT 0x00
|
|
mask P_DATAIN IOI
|
|
mask P_COMMAND CDI
|
|
mask P_MESGOUT CDI|MSGI
|
|
mask P_STATUS CDI|IOI
|
|
mask P_MESGIN CDI|IOI|MSGI
|
|
mask P_BUSFREE 0x01
|
|
}
|
|
MSGIN_EXT_LEN {
|
|
size 1
|
|
}
|
|
MSGIN_EXT_OPCODE {
|
|
size 1
|
|
}
|
|
/*
|
|
* location 3, stores the last
|
|
* byte of an extended message if
|
|
* it passes the two bytes of space
|
|
* we allow now. This byte isn't
|
|
* used for anything, it just makes
|
|
* the code shorter for tossing
|
|
* extra bytes.
|
|
*/
|
|
MSGIN_EXT_BYTES {
|
|
size 3
|
|
}
|
|
/*
|
|
* head of list of SCBs that are
|
|
* disconnected. Used for SCB
|
|
* paging.
|
|
*/
|
|
DISCONNECTED_SCBH {
|
|
size 1
|
|
}
|
|
/*
|
|
* head of list of SCBs that are
|
|
* not in use. Used for SCB paging.
|
|
*/
|
|
FREE_SCBH {
|
|
size 1
|
|
}
|
|
HSCB_ADDR {
|
|
size 4
|
|
}
|
|
CUR_SCBID {
|
|
size 1
|
|
}
|
|
ARG_1 {
|
|
size 1
|
|
mask SEND_MSG 0x80
|
|
mask SEND_SENSE 0x40
|
|
mask SEND_REJ 0x20
|
|
alias RETURN_1
|
|
}
|
|
/*
|
|
* These are reserved registers in the card's scratch ram. Some of
|
|
* the values are specified in the AHA2742 technical reference manual
|
|
* and are initialized by the BIOS at boot time.
|
|
*/
|
|
SCSICONF {
|
|
address 0x05a
|
|
size 1
|
|
bit RESET_SCSI 0x40
|
|
}
|
|
HOSTCONF {
|
|
address 0x05d
|
|
size 1
|
|
}
|
|
HA_274_BIOSCTRL {
|
|
address 0x05f
|
|
size 1
|
|
mask BIOSMODE 0x30
|
|
mask BIOSDISABLED 0x30
|
|
bit CHANNEL_B_PRIMARY 0x08
|
|
}
|
|
}
|
|
|
|
const SCB_LIST_NULL 0xff
|
|
|
|
|
|
/* WDTR Message values */
|
|
const BUS_8_BIT 0x00
|
|
const BUS_16_BIT 0x01
|
|
const BUS_32_BIT 0x02
|
|
const MAX_OFFSET_8BIT 0x0f
|
|
const MAX_OFFSET_16BIT 0x08
|