45f6d66569
most kernels before FreeBSD 9.0. Remove such modules and respective kernel options: atadisk, ataraid, atapicd, atapifd, atapist, atapicam. Remove the atacontrol utility and some man pages. Remove useless now options ATA_CAM. No objections: current@, stable@ MFC after: never
898 lines
26 KiB
C
898 lines
26 KiB
C
/*-
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ata.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/endian.h>
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#include <sys/ata.h>
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#include <sys/conf.h>
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#include <sys/ctype.h>
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#include <sys/bus.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-pci.h>
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#include <ata_if.h>
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/* prototypes */
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static int ata_generic_status(device_t dev);
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static int ata_wait(struct ata_channel *ch, int unit, u_int8_t);
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static void ata_pio_read(struct ata_request *, int);
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static void ata_pio_write(struct ata_request *, int);
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static void ata_tf_read(struct ata_request *);
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static void ata_tf_write(struct ata_request *);
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/*
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* low level ATA functions
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*/
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void
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ata_generic_hw(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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ch->hw.begin_transaction = ata_begin_transaction;
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ch->hw.end_transaction = ata_end_transaction;
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ch->hw.status = ata_generic_status;
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ch->hw.softreset = NULL;
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ch->hw.command = ata_generic_command;
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ch->hw.tf_read = ata_tf_read;
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ch->hw.tf_write = ata_tf_write;
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ch->hw.pm_read = NULL;
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ch->hw.pm_write = NULL;
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}
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/* must be called with ATA channel locked and state_mtx held */
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int
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ata_begin_transaction(struct ata_request *request)
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{
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struct ata_channel *ch = device_get_softc(request->parent);
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int dummy, error;
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ATA_DEBUG_RQ(request, "begin transaction");
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/* disable ATAPI DMA writes if HW doesn't support it */
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if ((ch->flags & ATA_NO_ATAPI_DMA) &&
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(request->flags & ATA_R_ATAPI) == ATA_R_ATAPI)
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request->flags &= ~ATA_R_DMA;
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if ((ch->flags & ATA_ATAPI_DMA_RO) &&
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((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
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(ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
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request->flags &= ~ATA_R_DMA;
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switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
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/* ATA PIO data transfer and control commands */
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default:
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{
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/* record command direction here as our request might be gone later */
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int write = (request->flags & ATA_R_WRITE);
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/* issue command */
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if (ch->hw.command(request)) {
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device_printf(request->parent, "error issuing %s command\n",
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ata_cmd2str(request));
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request->result = EIO;
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goto begin_finished;
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}
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/* device reset doesn't interrupt */
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if (request->u.ata.command == ATA_DEVICE_RESET) {
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int timeout = 1000000;
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do {
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DELAY(10);
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request->status = ATA_IDX_INB(ch, ATA_STATUS);
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} while (request->status & ATA_S_BUSY && timeout--);
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if (request->status & ATA_S_ERROR)
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request->error = ATA_IDX_INB(ch, ATA_ERROR);
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ch->hw.tf_read(request);
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goto begin_finished;
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}
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/* if write command output the data */
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if (write) {
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if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) {
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device_printf(request->parent,
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"timeout waiting for write DRQ\n");
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request->result = EIO;
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goto begin_finished;
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}
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ata_pio_write(request, request->transfersize);
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}
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}
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goto begin_continue;
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/* ATA DMA data transfer commands */
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case ATA_R_DMA:
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/* check sanity, setup SG list and DMA engine */
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if ((error = ch->dma.load(request, NULL, &dummy))) {
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device_printf(request->parent, "setting up DMA failed\n");
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request->result = error;
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goto begin_finished;
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}
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/* start DMA engine if necessary */
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if ((ch->flags & ATA_DMA_BEFORE_CMD) &&
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ch->dma.start && ch->dma.start(request)) {
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device_printf(request->parent, "error starting DMA\n");
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request->result = EIO;
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goto begin_finished;
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}
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/* issue command */
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if (ch->hw.command(request)) {
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device_printf(request->parent, "error issuing %s command\n",
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ata_cmd2str(request));
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request->result = EIO;
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goto begin_finished;
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}
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/* start DMA engine */
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if (!(ch->flags & ATA_DMA_BEFORE_CMD) &&
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ch->dma.start && ch->dma.start(request)) {
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device_printf(request->parent, "error starting DMA\n");
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request->result = EIO;
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goto begin_finished;
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}
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goto begin_continue;
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/* ATAPI PIO commands */
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case ATA_R_ATAPI:
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/* is this just a POLL DSC command ? */
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if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
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ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit));
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DELAY(10);
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if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
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request->result = EBUSY;
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goto begin_finished;
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}
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/* start ATAPI operation */
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if (ch->hw.command(request)) {
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device_printf(request->parent, "error issuing ATA PACKET command\n");
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request->result = EIO;
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goto begin_finished;
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}
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goto begin_continue;
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/* ATAPI DMA commands */
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case ATA_R_ATAPI|ATA_R_DMA:
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/* is this just a POLL DSC command ? */
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if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
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ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit));
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DELAY(10);
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if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
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request->result = EBUSY;
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goto begin_finished;
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}
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/* check sanity, setup SG list and DMA engine */
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if ((error = ch->dma.load(request, NULL, &dummy))) {
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device_printf(request->parent, "setting up DMA failed\n");
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request->result = error;
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goto begin_finished;
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}
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/* start ATAPI operation */
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if (ch->hw.command(request)) {
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device_printf(request->parent, "error issuing ATA PACKET command\n");
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request->result = EIO;
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goto begin_finished;
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}
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/* start DMA engine */
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if (ch->dma.start && ch->dma.start(request)) {
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request->result = EIO;
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goto begin_finished;
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}
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goto begin_continue;
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}
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/* NOT REACHED */
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printf("ata_begin_transaction OOPS!!!\n");
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begin_finished:
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if (ch->dma.unload) {
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ch->dma.unload(request);
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}
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return ATA_OP_FINISHED;
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begin_continue:
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callout_reset(&request->callout, request->timeout * hz,
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(timeout_t*)ata_timeout, request);
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return ATA_OP_CONTINUES;
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}
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/* must be called with ATA channel locked and state_mtx held */
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int
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ata_end_transaction(struct ata_request *request)
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{
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struct ata_channel *ch = device_get_softc(request->parent);
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int length;
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ATA_DEBUG_RQ(request, "end transaction");
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/* clear interrupt and get status */
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request->status = ATA_IDX_INB(ch, ATA_STATUS);
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switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
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/* ATA PIO data transfer and control commands */
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default:
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/* on timeouts we have no data or anything so just return */
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if (request->flags & ATA_R_TIMEOUT)
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goto end_finished;
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/* Read back registers to the request struct. */
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if ((request->status & ATA_S_ERROR) ||
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(request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) {
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ch->hw.tf_read(request);
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}
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/* if we got an error we are done with the HW */
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if (request->status & ATA_S_ERROR) {
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request->error = ATA_IDX_INB(ch, ATA_ERROR);
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goto end_finished;
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}
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/* are we moving data ? */
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if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
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/* if read data get it */
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if (request->flags & ATA_R_READ) {
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int flags = ATA_S_DRQ;
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if (request->u.ata.command != ATA_ATAPI_IDENTIFY)
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flags |= ATA_S_READY;
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if (ata_wait(ch, request->unit, flags) < 0) {
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device_printf(request->parent,
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"timeout waiting for read DRQ\n");
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request->result = EIO;
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goto end_finished;
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}
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ata_pio_read(request, request->transfersize);
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}
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/* update how far we've gotten */
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request->donecount += request->transfersize;
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/* do we need a scoop more ? */
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if (request->bytecount > request->donecount) {
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/* set this transfer size according to HW capabilities */
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request->transfersize =
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min((request->bytecount - request->donecount),
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request->transfersize);
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/* if data write command, output the data */
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if (request->flags & ATA_R_WRITE) {
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/* if we get an error here we are done with the HW */
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if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) {
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device_printf(request->parent,
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"timeout waiting for write DRQ\n");
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request->status = ATA_IDX_INB(ch, ATA_STATUS);
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goto end_finished;
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}
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/* output data and return waiting for new interrupt */
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ata_pio_write(request, request->transfersize);
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goto end_continue;
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}
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/* if data read command, return & wait for interrupt */
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if (request->flags & ATA_R_READ)
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goto end_continue;
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}
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}
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/* done with HW */
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goto end_finished;
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/* ATA DMA data transfer commands */
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case ATA_R_DMA:
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/* stop DMA engine and get status */
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if (ch->dma.stop)
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request->dma->status = ch->dma.stop(request);
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/* did we get error or data */
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if (request->status & ATA_S_ERROR)
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request->error = ATA_IDX_INB(ch, ATA_ERROR);
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else if (request->dma->status & ATA_BMSTAT_ERROR)
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request->status |= ATA_S_ERROR;
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else if (!(request->flags & ATA_R_TIMEOUT))
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request->donecount = request->bytecount;
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/* Read back registers to the request struct. */
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if ((request->status & ATA_S_ERROR) ||
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(request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) {
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ch->hw.tf_read(request);
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}
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/* release SG list etc */
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ch->dma.unload(request);
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/* done with HW */
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goto end_finished;
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/* ATAPI PIO commands */
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case ATA_R_ATAPI:
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length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
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/* on timeouts we have no data or anything so just return */
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if (request->flags & ATA_R_TIMEOUT)
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goto end_finished;
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switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
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(request->status & ATA_S_DRQ)) {
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case ATAPI_P_CMDOUT:
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/* this seems to be needed for some (slow) devices */
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DELAY(10);
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if (!(request->status & ATA_S_DRQ)) {
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device_printf(request->parent, "command interrupt without DRQ\n");
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request->status = ATA_S_ERROR;
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goto end_finished;
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}
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ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
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(request->flags & ATA_R_ATAPI16) ? 8 : 6);
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/* return wait for interrupt */
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goto end_continue;
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case ATAPI_P_WRITE:
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if (request->flags & ATA_R_READ) {
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request->status = ATA_S_ERROR;
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device_printf(request->parent,
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"%s trying to write on read buffer\n",
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ata_cmd2str(request));
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goto end_finished;
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}
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ata_pio_write(request, length);
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request->donecount += length;
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/* set next transfer size according to HW capabilities */
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request->transfersize = min((request->bytecount-request->donecount),
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request->transfersize);
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/* return wait for interrupt */
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goto end_continue;
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case ATAPI_P_READ:
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if (request->flags & ATA_R_WRITE) {
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request->status = ATA_S_ERROR;
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device_printf(request->parent,
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"%s trying to read on write buffer\n",
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ata_cmd2str(request));
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goto end_finished;
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}
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ata_pio_read(request, length);
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request->donecount += length;
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/* set next transfer size according to HW capabilities */
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request->transfersize = min((request->bytecount-request->donecount),
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request->transfersize);
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/* return wait for interrupt */
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goto end_continue;
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case ATAPI_P_DONEDRQ:
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device_printf(request->parent,
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"WARNING - %s DONEDRQ non conformant device\n",
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ata_cmd2str(request));
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if (request->flags & ATA_R_READ) {
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ata_pio_read(request, length);
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request->donecount += length;
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}
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else if (request->flags & ATA_R_WRITE) {
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ata_pio_write(request, length);
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request->donecount += length;
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}
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else
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request->status = ATA_S_ERROR;
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/* FALLTHROUGH */
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case ATAPI_P_ABORT:
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case ATAPI_P_DONE:
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if (request->status & (ATA_S_ERROR | ATA_S_DWF))
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request->error = ATA_IDX_INB(ch, ATA_ERROR);
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goto end_finished;
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default:
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device_printf(request->parent, "unknown transfer phase\n");
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request->status = ATA_S_ERROR;
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}
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/* done with HW */
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goto end_finished;
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/* ATAPI DMA commands */
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case ATA_R_ATAPI|ATA_R_DMA:
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/* stop DMA engine and get status */
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if (ch->dma.stop)
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request->dma->status = ch->dma.stop(request);
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/* did we get error or data */
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if (request->status & (ATA_S_ERROR | ATA_S_DWF))
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request->error = ATA_IDX_INB(ch, ATA_ERROR);
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else if (request->dma->status & ATA_BMSTAT_ERROR)
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request->status |= ATA_S_ERROR;
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else if (!(request->flags & ATA_R_TIMEOUT))
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request->donecount = request->bytecount;
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/* release SG list etc */
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ch->dma.unload(request);
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/* done with HW */
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goto end_finished;
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}
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/* NOT REACHED */
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printf("ata_end_transaction OOPS!!\n");
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end_finished:
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callout_stop(&request->callout);
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return ATA_OP_FINISHED;
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end_continue:
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return ATA_OP_CONTINUES;
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}
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/* must be called with ATA channel locked and state_mtx held */
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void
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ata_generic_reset(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0;
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u_int8_t err = 0, lsb = 0, msb = 0;
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int mask = 0, timeout;
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/* do we have any signs of ATA/ATAPI HW being present ? */
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ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER));
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DELAY(10);
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ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
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if (((ostat0 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) &&
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ostat0 != 0xa5) {
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stat0 = ATA_S_BUSY;
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mask |= 0x01;
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}
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/* in some setups we dont want to test for a slave */
|
|
if (!(ch->flags & ATA_NO_SLAVE)) {
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE));
|
|
DELAY(10);
|
|
ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
|
|
if (((ostat1 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) &&
|
|
ostat1 != 0xa5) {
|
|
stat1 = ATA_S_BUSY;
|
|
mask |= 0x02;
|
|
}
|
|
}
|
|
|
|
if (bootverbose)
|
|
device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
|
|
mask, ostat0, ostat1);
|
|
|
|
/* if nothing showed up there is no need to get any further */
|
|
/* XXX SOS is that too strong?, we just might loose devices here */
|
|
ch->devices = 0;
|
|
if (!mask)
|
|
return;
|
|
|
|
/* reset (both) devices on this channel */
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER));
|
|
DELAY(10);
|
|
ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
|
|
ata_udelay(10000);
|
|
ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
|
|
ata_udelay(100000);
|
|
ATA_IDX_INB(ch, ATA_ERROR);
|
|
|
|
/* wait for BUSY to go inactive */
|
|
for (timeout = 0; timeout < 310; timeout++) {
|
|
if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) {
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER));
|
|
DELAY(10);
|
|
if (ch->flags & ATA_STATUS_IS_LONG)
|
|
stat0 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff;
|
|
else
|
|
stat0 = ATA_IDX_INB(ch, ATA_STATUS);
|
|
err = ATA_IDX_INB(ch, ATA_ERROR);
|
|
lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
|
|
msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
|
|
if (bootverbose)
|
|
device_printf(dev,
|
|
"stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
|
|
stat0, err, lsb, msb);
|
|
if (stat0 == err && lsb == err && msb == err &&
|
|
timeout > (stat0 & ATA_S_BUSY ? 100 : 10))
|
|
mask &= ~0x01;
|
|
if (!(stat0 & ATA_S_BUSY)) {
|
|
if ((err & 0x7f) == ATA_E_ILI) {
|
|
if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
|
|
ch->devices |= ATA_ATAPI_MASTER;
|
|
}
|
|
else if (lsb == 0 && msb == 0 && (stat0 & ATA_S_READY)) {
|
|
ch->devices |= ATA_ATA_MASTER;
|
|
}
|
|
}
|
|
else if ((stat0 & 0x0f) && err == lsb && err == msb) {
|
|
stat0 |= ATA_S_BUSY;
|
|
}
|
|
}
|
|
}
|
|
|
|
if ((mask & 0x02) && (stat1 & ATA_S_BUSY) &&
|
|
!((mask & 0x01) && (stat0 & ATA_S_BUSY))) {
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE));
|
|
DELAY(10);
|
|
if (ch->flags & ATA_STATUS_IS_LONG)
|
|
stat1 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff;
|
|
else
|
|
stat1 = ATA_IDX_INB(ch, ATA_STATUS);
|
|
err = ATA_IDX_INB(ch, ATA_ERROR);
|
|
lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
|
|
msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
|
|
if (bootverbose)
|
|
device_printf(dev,
|
|
"stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
|
|
stat1, err, lsb, msb);
|
|
if (stat1 == err && lsb == err && msb == err &&
|
|
timeout > (stat1 & ATA_S_BUSY ? 100 : 10))
|
|
mask &= ~0x02;
|
|
if (!(stat1 & ATA_S_BUSY)) {
|
|
if ((err & 0x7f) == ATA_E_ILI) {
|
|
if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
|
|
ch->devices |= ATA_ATAPI_SLAVE;
|
|
}
|
|
else if (lsb == 0 && msb == 0 && (stat1 & ATA_S_READY)) {
|
|
ch->devices |= ATA_ATA_SLAVE;
|
|
}
|
|
}
|
|
else if ((stat1 & 0x0f) && err == lsb && err == msb) {
|
|
stat1 |= ATA_S_BUSY;
|
|
}
|
|
}
|
|
}
|
|
|
|
if ((ch->flags & ATA_KNOWN_PRESENCE) == 0 &&
|
|
timeout > ((mask == 0x03) ? 20 : 10)) {
|
|
if ((mask & 0x01) && stat0 == 0xff)
|
|
mask &= ~0x01;
|
|
if ((mask & 0x02) && stat1 == 0xff)
|
|
mask &= ~0x02;
|
|
}
|
|
if (((mask & 0x01) == 0 || !(stat0 & ATA_S_BUSY)) &&
|
|
((mask & 0x02) == 0 || !(stat1 & ATA_S_BUSY)))
|
|
break;
|
|
ata_udelay(100000);
|
|
}
|
|
|
|
if (bootverbose)
|
|
device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n",
|
|
stat0, stat1, ch->devices);
|
|
}
|
|
|
|
/* must be called with ATA channel locked and state_mtx held */
|
|
int
|
|
ata_generic_status(device_t dev)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(dev);
|
|
|
|
if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
|
|
DELAY(100);
|
|
if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
ata_wait(struct ata_channel *ch, int unit, u_int8_t mask)
|
|
{
|
|
u_int8_t status;
|
|
int timeout = 0;
|
|
|
|
DELAY(1);
|
|
|
|
/* wait at max 1 second for device to get !BUSY */
|
|
while (timeout < 1000000) {
|
|
status = ATA_IDX_INB(ch, ATA_ALTSTAT);
|
|
|
|
/* if drive fails status, reselect the drive and try again */
|
|
if (status == 0xff) {
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(unit));
|
|
timeout += 1000;
|
|
DELAY(1000);
|
|
continue;
|
|
}
|
|
|
|
/* are we done ? */
|
|
if (!(status & ATA_S_BUSY))
|
|
break;
|
|
|
|
if (timeout > 1000) {
|
|
timeout += 1000;
|
|
DELAY(1000);
|
|
}
|
|
else {
|
|
timeout += 10;
|
|
DELAY(10);
|
|
}
|
|
}
|
|
if (timeout >= 1000000)
|
|
return -2;
|
|
if (!mask)
|
|
return (status & ATA_S_ERROR);
|
|
|
|
DELAY(1);
|
|
|
|
/* wait 50 msec for bits wanted */
|
|
timeout = 5000;
|
|
while (timeout--) {
|
|
status = ATA_IDX_INB(ch, ATA_ALTSTAT);
|
|
if ((status & mask) == mask)
|
|
return (status & ATA_S_ERROR);
|
|
DELAY(10);
|
|
}
|
|
return -3;
|
|
}
|
|
|
|
int
|
|
ata_generic_command(struct ata_request *request)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(request->parent);
|
|
|
|
/* select device */
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit));
|
|
|
|
/* ready to issue command ? */
|
|
if (ata_wait(ch, request->unit, 0) < 0) {
|
|
device_printf(request->parent, "timeout waiting to issue command\n");
|
|
request->flags |= ATA_R_TIMEOUT;
|
|
return (-1);
|
|
}
|
|
|
|
/* enable interrupt */
|
|
ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
|
|
|
|
if (request->flags & ATA_R_ATAPI) {
|
|
int timeout = 5000;
|
|
int res;
|
|
|
|
/* issue packet command to controller */
|
|
if (request->flags & ATA_R_DMA) {
|
|
ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA);
|
|
ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0);
|
|
ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0);
|
|
}
|
|
else {
|
|
ATA_IDX_OUTB(ch, ATA_FEATURE, 0);
|
|
ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize);
|
|
ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8);
|
|
}
|
|
ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD);
|
|
|
|
/* command interrupt device ? just return and wait for interrupt */
|
|
if (request->flags & ATA_R_ATAPI_INTR)
|
|
return (0);
|
|
|
|
/* command processed ? */
|
|
res = ata_wait(ch, request->unit, 0);
|
|
if (res != 0) {
|
|
if (res < 0) {
|
|
device_printf(request->parent,
|
|
"timeout waiting for PACKET command\n");
|
|
request->flags |= ATA_R_TIMEOUT;
|
|
}
|
|
return (-1);
|
|
}
|
|
/* wait for ready to write ATAPI command block */
|
|
while (timeout--) {
|
|
int reason = ATA_IDX_INB(ch, ATA_IREASON);
|
|
int status = ATA_IDX_INB(ch, ATA_STATUS);
|
|
|
|
if (((reason & (ATA_I_CMD | ATA_I_IN)) |
|
|
(status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
|
|
break;
|
|
DELAY(20);
|
|
}
|
|
if (timeout <= 0) {
|
|
device_printf(request->parent,
|
|
"timeout waiting for ATAPI ready\n");
|
|
request->flags |= ATA_R_TIMEOUT;
|
|
return (-1);
|
|
}
|
|
|
|
/* this seems to be needed for some (slow) devices */
|
|
DELAY(10);
|
|
|
|
/* output command block */
|
|
ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
|
|
(request->flags & ATA_R_ATAPI16) ? 8 : 6);
|
|
}
|
|
else {
|
|
ch->hw.tf_write(request);
|
|
|
|
/* issue command to controller */
|
|
ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
ata_tf_read(struct ata_request *request)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(request->parent);
|
|
|
|
if (request->flags & ATA_R_48BIT) {
|
|
ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB);
|
|
request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8);
|
|
request->u.ata.lba =
|
|
((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) |
|
|
((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) |
|
|
((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40);
|
|
|
|
ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
|
|
request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT);
|
|
request->u.ata.lba |=
|
|
(ATA_IDX_INB(ch, ATA_SECTOR) |
|
|
(ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
|
|
(ATA_IDX_INB(ch, ATA_CYL_MSB) << 16));
|
|
}
|
|
else {
|
|
request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
|
|
request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
|
|
(ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
|
|
(ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) |
|
|
((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24);
|
|
}
|
|
}
|
|
|
|
static void
|
|
ata_tf_write(struct ata_request *request)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(request->parent);
|
|
|
|
if (request->flags & ATA_R_48BIT) {
|
|
ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8);
|
|
ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
|
|
ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8);
|
|
ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
|
|
ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24);
|
|
ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
|
|
ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32);
|
|
ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
|
|
ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40);
|
|
ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
|
|
}
|
|
else {
|
|
ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
|
|
ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
|
|
ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
|
|
ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
|
|
ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE,
|
|
ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
|
|
((request->u.ata.lba >> 24) & 0x0f));
|
|
}
|
|
}
|
|
|
|
static void
|
|
ata_pio_read(struct ata_request *request, int length)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(request->parent);
|
|
uint8_t *addr;
|
|
int size = min(request->transfersize, length);
|
|
int resid;
|
|
uint8_t buf[2] __aligned(sizeof(int16_t));
|
|
#ifndef __NO_STRICT_ALIGNMENT
|
|
int i;
|
|
#endif
|
|
|
|
addr = (uint8_t *)request->data + request->donecount;
|
|
if (__predict_false(ch->flags & ATA_USE_16BIT ||
|
|
(size % sizeof(int32_t)) || ((uintptr_t)addr % sizeof(int32_t)))) {
|
|
#ifndef __NO_STRICT_ALIGNMENT
|
|
if (__predict_false((uintptr_t)addr % sizeof(int16_t))) {
|
|
for (i = 0, resid = size & ~1; resid > 0; resid -=
|
|
sizeof(int16_t)) {
|
|
*(uint16_t *)&buf = ATA_IDX_INW_STRM(ch, ATA_DATA);
|
|
addr[i++] = buf[0];
|
|
addr[i++] = buf[1];
|
|
}
|
|
} else
|
|
#endif
|
|
ATA_IDX_INSW_STRM(ch, ATA_DATA, (void*)addr, size /
|
|
sizeof(int16_t));
|
|
if (size & 1) {
|
|
*(uint16_t *)&buf = ATA_IDX_INW_STRM(ch, ATA_DATA);
|
|
(addr + (size & ~1))[0] = buf[0];
|
|
}
|
|
} else
|
|
ATA_IDX_INSL_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int32_t));
|
|
|
|
if (request->transfersize < length) {
|
|
device_printf(request->parent, "WARNING - %s read data overrun %d>%d\n",
|
|
ata_cmd2str(request), length, request->transfersize);
|
|
for (resid = request->transfersize + (size & 1); resid < length;
|
|
resid += sizeof(int16_t))
|
|
ATA_IDX_INW(ch, ATA_DATA);
|
|
}
|
|
}
|
|
|
|
static void
|
|
ata_pio_write(struct ata_request *request, int length)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(request->parent);
|
|
uint8_t *addr;
|
|
int size = min(request->transfersize, length);
|
|
int resid;
|
|
uint8_t buf[2] __aligned(sizeof(int16_t));
|
|
#ifndef __NO_STRICT_ALIGNMENT
|
|
int i;
|
|
#endif
|
|
|
|
size = min(request->transfersize, length);
|
|
addr = (uint8_t *)request->data + request->donecount;
|
|
if (__predict_false(ch->flags & ATA_USE_16BIT ||
|
|
(size % sizeof(int32_t)) || ((uintptr_t)addr % sizeof(int32_t)))) {
|
|
#ifndef __NO_STRICT_ALIGNMENT
|
|
if (__predict_false((uintptr_t)addr % sizeof(int16_t))) {
|
|
for (i = 0, resid = size & ~1; resid > 0; resid -=
|
|
sizeof(int16_t)) {
|
|
buf[0] = addr[i++];
|
|
buf[1] = addr[i++];
|
|
ATA_IDX_OUTW_STRM(ch, ATA_DATA, *(uint16_t *)&buf);
|
|
}
|
|
} else
|
|
#endif
|
|
ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (void*)addr, size /
|
|
sizeof(int16_t));
|
|
if (size & 1) {
|
|
buf[0] = (addr + (size & ~1))[0];
|
|
ATA_IDX_OUTW_STRM(ch, ATA_DATA, *(uint16_t *)&buf);
|
|
}
|
|
} else
|
|
ATA_IDX_OUTSL_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int32_t));
|
|
|
|
if (request->transfersize < length) {
|
|
device_printf(request->parent, "WARNING - %s write data underrun %d>%d\n",
|
|
ata_cmd2str(request), length, request->transfersize);
|
|
for (resid = request->transfersize + (size & 1); resid < length;
|
|
resid += sizeof(int16_t))
|
|
ATA_IDX_OUTW(ch, ATA_DATA, 0);
|
|
}
|
|
}
|