966 lines
34 KiB
C
966 lines
34 KiB
C
/*
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* File Name : trm.h
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*
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* Tekram DC395U/UW/F ,DC315/U
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* PCI SCSI Bus Master Host Adapter Device Driver
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* (SCSI chip set used Tekram ASIC TRM-S1040)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef trm_H
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#define trm_H
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/* SCSI CAM */
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#define TRM_TRANS_CUR 0x01 /* Modify current neogtiation status */
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#define TRM_TRANS_ACTIVE 0x03 /* Assume this is the active target */
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#define TRM_TRANS_GOAL 0x04 /* Modify negotiation goal */
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#define TRM_TRANS_USER 0x08 /* Modify user negotiation settings */
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struct trm_transinfo {
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u_int8_t width;
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u_int8_t period;
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u_int8_t offset;
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};
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struct trm_target_info {
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u_int8_t disc_tag; /* bits define..... */
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#define TRM_CUR_DISCENB 0x01 /* current setting disconnect enable */
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#define TRM_CUR_TAGENB 0x02 /* current setting tag command Q enable */
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#define TRM_USR_DISCENB 0x04 /* user adapter device setting disconnect enable */
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#define TRM_USR_TAGENB 0x08 /* user adapter device setting tag command Q enable*/
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struct trm_transinfo current; /* info of current */
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struct trm_transinfo goal; /* info of after negotiating */
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struct trm_transinfo user; /* info of user adapter device setting */
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};
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/*
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* SCSI CAM **
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*/
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/*
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* bus_dma_segment_t
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*
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* Describes a single contiguous DMA transaction. Values
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* are suitable for programming into DMA registers.
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*
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*typedef struct bus_dma_segment
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*{
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* bus_addr_t ds_addr; // DMA address
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* bus_size_t ds_len; // length of transfer
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*} bus_dma_segment_t;
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*/
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/*;----------------------Segment Entry------------------------------------*/
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typedef struct _SGentry {
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u_long address;
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u_long length;
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} SGentry, *PSEG;
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/*
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*-----------------------------------------------------------------------
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* feature of chip set MAX value
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*-----------------------------------------------------------------------
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*/
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#define MAX_ADAPTER_NUM 4
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#define MAX_DEVICES 16
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#define MAX_SG_LISTENTRY 32
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#define MAX_TARGETS 16
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#define MAX_TAGS_CMD_QUEUE 32 /* MAX_CMD_QUEUE 20*/
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#define MAX_CMD_PER_LUN 32
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#define MAX_SRB_CNT MAX_CMD_PER_LUN*4
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#define MAX_START_JOB MAX_CMD_PER_LUN*4
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#define TRM_NSEG (btoc(MAXPHYS) + 1)
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#define TRM_MAXTRANSFER_SIZE 0xFFFFFF /* restricted by 24 bit counter */
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#define PAGELEN 4096
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#define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40MHz) */
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/*
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* CAM ccb
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* Union of all CCB types for kernel space allocation. This union should
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* never be used for manipulating CCBs - its only use is for the allocation
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* and deallocation of raw CCB space and is the return type of xpt_ccb_alloc
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* and the argument to xpt_ccb_free.
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*
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*union ccb {
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* struct ccb_hdr ccb_h; // For convenience
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* struct ccb_scsiio csio;
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* struct ccb_getdev cgd;
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* struct ccb_getdevlist cgdl;
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* struct ccb_pathinq cpi;
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* struct ccb_relsim crs;
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* struct ccb_setasync csa;
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* struct ccb_setdev csd;
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* struct ccb_dev_match cdm;
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* struct ccb_trans_settings cts;
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* struct ccb_calc_geometry ccg;
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* struct ccb_abort cab;
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* struct ccb_resetbus crb;
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* struct ccb_resetdev crd;
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* struct ccb_termio tio;
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* struct ccb_accept_tio atio;
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* struct ccb_scsiio ctio;
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* struct ccb_en_lun cel;
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* struct ccb_immed_notify cin;
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* struct ccb_notify_ack cna;
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* struct ccb_eng_inq cei;
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* struct ccb_eng_exec cee;
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* struct ccb_rescan crcn;
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* struct ccb_debug cdbg;
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* };
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*/
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/*
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*-----------------------------------------------------------------------
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* SCSI Request Block
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*-----------------------------------------------------------------------
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*/
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struct _SRB {
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u_int8_t CmdBlock[12];
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u_long Segment0[2];
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u_long Segment1[2];
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u_long PhysSRB;
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struct _SRB *pNextSRB;
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struct _DCB *pSRBDCB;
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SGentry SegmentX[MAX_SG_LISTENTRY];
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SGentry SgSenseTemp;
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/*
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* CAM ccb
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*/
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union ccb *pccb;
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bus_dmamap_t dmamap;
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PSEG SRBSGListPointer; /* scatter gather list */
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u_long SRBTotalXferLength;
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u_long SRBSGPhyAddr; /* a segment starting address */
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u_int16_t SRBState;
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u_int8_t * pMsgPtr;
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u_int8_t SRBSGCount;
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u_int8_t SRBSGIndex;
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u_int8_t MsgInBuf[6];
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u_int8_t MsgOutBuf[6];
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u_int8_t AdaptStatus;
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u_int8_t TargetStatus;
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u_int8_t MsgCnt;
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u_int8_t TagNumber;
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u_int8_t SRBStatus;
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u_int8_t RetryCnt;
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/* b0-AutoReqSense,b6-Read,b7-write */
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/* b4-settimeout,b5-Residual valid */
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u_int8_t SRBFlag;
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u_int8_t ScsiCmdLen;
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u_int8_t ScsiPhase;
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u_int8_t Reserved[3]; /*;for dword alignment */
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};
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typedef struct _SRB TRM_SRB, *PSRB;
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/*
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*-----------------------------------------------------------------------
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* Device Control Block
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*-----------------------------------------------------------------------
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*/
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struct _DCB
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{
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struct _DCB *pNextDCB;
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struct _ACB *pDCBACB;
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PSRB pWaitingSRB;
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PSRB pWaitLastSRB;
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PSRB pGoingSRB;
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PSRB pGoingLastSRB;
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PSRB pActiveSRB;
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PSRB RevSRB;
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u_long TagMask;
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u_int16_t GoingSRBCnt;
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u_int16_t WaitSRBCnt;
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u_int8_t TargetID; /*; SCSI Target ID (SCSI Only) */
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u_int8_t TargetLUN; /*; SCSI Log. Unit (SCSI Only) */
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u_int8_t DCBFlag;
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u_int8_t DevType;
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u_int8_t SyncMode; /* mode ? (1 sync):(0 async) */
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u_int8_t MaxNegoPeriod; /* for nego. */
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u_int8_t SyncPeriod; /* for reg. */
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u_int8_t SyncOffset; /* for reg. and nego.(low nibble) */
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struct trm_target_info tinfo; /* 10 bytes */
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u_int16_t MaxCommand;
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u_int8_t DevMode;
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u_int8_t AdpMode;
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u_int8_t IdentifyMsg;
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u_int8_t Reserved[3]; /*for dword alignment */
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};
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typedef struct _DCB TRM_DCB, *PDCB;
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/*
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*-----------------------------------------------------------------------
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* Adapter Control Block
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*-----------------------------------------------------------------------
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*/
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struct _ACB
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{
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bus_space_tag_t tag;
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bus_space_handle_t bsh;
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bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
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struct _ACB *pNextACB;
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/*
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* CAM SIM/XPT
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*/
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struct cam_sim *psim;
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struct cam_path *ppath;
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TRM_SRB SRB_array[MAX_SRB_CNT]; /* */
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TRM_SRB TmpSRB;
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PSRB pTmpSRB;
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PSRB RevSRB;
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PSRB pFreeSRB;
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PDCB pActiveDCB;
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PDCB pLinkDCB;
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PDCB pDCBRunRobin;
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PDCB pDCB[16][8];
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u_int16_t max_id;
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u_int16_t max_lun;
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u_int16_t IOPortBase;
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u_int16_t AdapterUnit; /*; nth Adapter this driver */
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u_int8_t msgin123[4];
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u_int8_t scan_devices[16][8];
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u_int8_t AdaptSCSIID; /*; Adapter SCSI Target ID */
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u_int8_t AdaptSCSILUN; /*; Adapter SCSI LUN */
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u_int8_t DeviceCnt;
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u_int8_t ACBFlag;
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u_int8_t TagMaxNum;
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u_int8_t Config;
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u_int8_t Reserved[2]; /* for dword alignment */
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};
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typedef struct _ACB TRM_ACB, *PACB;
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/*
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* ----SRB State machine definition
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*/
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#define SRB_FREE 0x0000
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#define SRB_WAIT 0x0001
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#define SRB_READY 0x0002
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#define SRB_MSGOUT 0x0004 /*arbitration+msg_out 1st byte*/
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#define SRB_MSGIN 0x0008
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#define SRB_EXTEND_MSGIN 0x0010
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#define SRB_COMMAND 0x0020
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#define SRB_START_ 0x0040 /*arbitration+msg_out+command_out*/
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#define SRB_DISCONNECT 0x0080
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#define SRB_DATA_XFER 0x0100
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#define SRB_XFERPAD 0x0200
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#define SRB_STATUS 0x0400
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#define SRB_COMPLETED 0x0800
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#define SRB_ABORT_SENT 0x1000
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#define SRB_DO_SYNC_NEGO 0x2000
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#define SRB_DO_WIDE_NEGO 0x4000
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#define SRB_UNEXPECT_RESEL 0x8000
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/*
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*
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* ACB Config
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*
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*/
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#define HCC_WIDE_CARD 0x20
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#define HCC_SCSI_RESET 0x10
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#define HCC_PARITY 0x08
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#define HCC_AUTOTERM 0x04
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#define HCC_LOW8TERM 0x02
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#define HCC_UP8TERM 0x01
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/*
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* ---ACB Flag
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*/
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#define RESET_DEV 0x00000001
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#define RESET_DETECT 0x00000002
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#define RESET_DONE 0x00000004
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/*
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* ---DCB Flag
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*/
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#define ABORT_DEV_ 0x00000001
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/*
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* ---SRB status
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*/
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#define SRB_OK 0x00000001
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#define ABORTION 0x00000002
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#define OVER_RUN 0x00000004
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#define UNDER_RUN 0x00000008
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#define PARITY_ERROR 0x00000010
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#define SRB_ERROR 0x00000020
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/*
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* ---SRB Flag
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*/
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#define DATAOUT 0x00000080
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#define DATAIN 0x00000040
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#define RESIDUAL_VALID 0x00000020
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#define ENABLE_TIMER 0x00000010
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#define RESET_DEV0 0x00000004
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#define ABORT_DEV 0x00000002
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#define AUTO_REQSENSE 0x00000001
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/*
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* ---Adapter status
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*/
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#define H_STATUS_GOOD 0x00
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#define H_SEL_TIMEOUT 0x11
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#define H_OVER_UNDER_RUN 0x12
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#define H_UNEXP_BUS_FREE 0x13
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#define H_TARGET_PHASE_F 0x14
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#define H_INVALID_CCB_OP 0x16
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#define H_LINK_CCB_BAD 0x17
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#define H_BAD_TARGET_DIR 0x18
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#define H_DUPLICATE_CCB 0x19
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#define H_BAD_CCB_OR_SG 0x1A
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#define H_ABORT 0x0FF
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/*
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* ---SCSI Status byte codes
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*/
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#define SCSI_STAT_GOOD 0x00 /*; Good status */
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#define SCSI_STAT_CHECKCOND 0x02 /*; SCSI Check Condition */
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#define SCSI_STAT_CONDMET 0x04 /*; Condition Met */
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#define SCSI_STAT_BUSY 0x08 /*; Target busy status */
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#define SCSI_STAT_INTER 0x10 /*; Intermediate status */
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#define SCSI_STAT_INTERCONDMET 0x14 /*; Intermediate condition met */
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#define SCSI_STAT_RESCONFLICT 0x18 /*; Reservation conflict */
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#define SCSI_STAT_CMDTERM 0x22 /*; Command Terminated */
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#define SCSI_STAT_QUEUEFULL 0x28 /*; Queue Full */
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#define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */
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#define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */
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#define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */
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/*
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* ---Sync_Mode
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*/
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#define SYNC_WIDE_TAG_ATNT_DISABLE 0x00000000
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#define SYNC_NEGO_ENABLE 0x00000001
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#define SYNC_NEGO_DONE 0x00000002
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#define WIDE_NEGO_ENABLE 0x00000004
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#define WIDE_NEGO_DONE 0x00000008
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#define EN_TAG_QUEUING 0x00000010
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#define EN_ATN_STOP 0x00000020
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#define SYNC_NEGO_OFFSET 15
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/*
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* ---SCSI bus phase
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*/
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#define SCSI_DATA_OUT_ 0
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#define SCSI_DATA_IN_ 1
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#define SCSI_COMMAND 2
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#define SCSI_STATUS_ 3
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#define SCSI_NOP0 4
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#define SCSI_NOP1 5
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#define SCSI_MSG_OUT 6
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#define SCSI_MSG_IN 7
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/*
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* ----SCSI MSG u_int8_t
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*/
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#define MSG_COMPLETE 0x00
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#define MSG_EXTENDED 0x01
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#define MSG_SAVE_PTR 0x02
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#define MSG_RESTORE_PTR 0x03
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#define MSG_DISCONNECT 0x04
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#define MSG_INITIATOR_ERROR 0x05
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#define MSG_ABORT 0x06
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#define MSG_REJECT_ 0x07
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#define MSG_NOP 0x08
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#define MSG_PARITY_ERROR 0x09
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#define MSG_LINK_CMD_COMPL 0x0A
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#define MSG_LINK_CMD_COMPL_FLG 0x0B
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#define MSG_BUS_RESET 0x0C
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#define MSG_ABORT_TAG 0x0D
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#define MSG_SIMPLE_QTAG 0x20
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#define MSG_HEAD_QTAG 0x21
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#define MSG_ORDER_QTAG 0x22
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#define MSG_IGNOREWIDE 0x23
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#define MSG_IDENTIFY 0x80
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#define MSG_HOST_ID 0xC0
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/* bus wide length */
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#define MSG_EXT_WDTR_BUS_8_BIT 0x00
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#define MSG_EXT_WDTR_BUS_16_BIT 0x01
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#define MSG_EXT_WDTR_BUS_32_BIT 0x02
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/*
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* ----SCSI STATUS u_int8_t
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*/
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#define STATUS_GOOD 0x00
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#define CHECK_CONDITION_ 0x02
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#define STATUS_BUSY 0x08
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#define STATUS_INTERMEDIATE 0x10
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#define RESERVE_CONFLICT 0x18
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/*
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* ---- cmd->result
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*/
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#define STATUS_MASK_ 0xFF
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#define MSG_MASK 0xFF00
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#define RETURN_MASK 0xFF0000
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/*
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* Inquiry Data format
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*/
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typedef struct _SCSIInqData { /* INQ */
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u_int8_t DevType; /* Periph Qualifier & Periph Dev Type */
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u_int8_t RMB_TypeMod; /* rem media bit & Dev Type Modifier */
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u_int8_t Vers; /* ISO, ECMA, & ANSI versions */
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u_int8_t RDF; /* AEN, TRMIOP, & response data format*/
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u_int8_t AddLen; /* length of additional data */
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u_int8_t Res1; /* reserved */
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u_int8_t Res2; /* reserved */
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u_int8_t Flags; /* RelADr,Wbus32,Wbus16,Sync,etc. */
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u_int8_t VendorID[8]; /* Vendor Identification */
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u_int8_t ProductID[16]; /* Product Identification */
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u_int8_t ProductRev[4]; /* Product Revision */
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} SCSI_INQDATA, *PSCSI_INQDATA;
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/*
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* Inquiry byte 0 masks
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*/
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#define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */
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#define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */
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/*
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* Inquiry byte 1 mask
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*/
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#define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */
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/*
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* Peripheral Device Type definitions
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*/
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#define SCSI_DASD 0x00 /* Direct-access Device */
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#define SCSI_SEQACESS 0x01 /* Sequential-access device */
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#define SCSI_PRINTER 0x02 /* Printer device */
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#define SCSI_PROCESSOR 0x03 /* Processor device */
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#define SCSI_WRITEONCE 0x04 /* Write-once device */
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#define SCSI_CDROM 0x05 /* CD-ROM device */
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#define SCSI_SCANNER 0x06 /* Scanner device */
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#define SCSI_OPTICAL 0x07 /* Optical memory device */
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#define SCSI_MEDCHGR 0x08 /* Medium changer device */
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#define SCSI_COMM 0x09 /* Communications device */
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#define SCSI_NODEV 0x1F /* Unknown or no device type */
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/*
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* Inquiry flag definitions (Inq data byte 7)
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*/
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#define SCSI_INQ_RELADR 0x80 /* device supports relative addressing*/
|
|
#define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */
|
|
#define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */
|
|
#define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */
|
|
#define SCSI_INQ_LINKED 0x08 /* device supports linked commands */
|
|
#define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */
|
|
#define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */
|
|
/*
|
|
*==========================================================
|
|
* EEPROM byte offset
|
|
*==========================================================
|
|
*/
|
|
typedef struct _EEprom {
|
|
u_int8_t EE_MODE1;
|
|
u_int8_t EE_SPEED;
|
|
u_int8_t xx1;
|
|
u_int8_t xx2;
|
|
} EEprom, *PEEprom;
|
|
|
|
#define EE_ADAPT_SCSI_ID 64
|
|
#define EE_MODE2 65
|
|
#define EE_DELAY 66
|
|
#define EE_TAG_CMD_NUM 67
|
|
|
|
/*
|
|
* EE_MODE1 bits definition
|
|
*/
|
|
#define PARITY_CHK_ 0x00000001
|
|
#define SYNC_NEGO_ 0x00000002
|
|
#define EN_DISCONNECT_ 0x00000004
|
|
#define SEND_START_ 0x00000008
|
|
#define TAG_QUEUING_ 0x00000010
|
|
|
|
/*
|
|
* EE_MODE2 bits definition
|
|
*/
|
|
#define MORE2_DRV 0x00000001
|
|
#define GREATER_1G 0x00000002
|
|
#define RST_SCSI_BUS 0x00000004
|
|
#define ACTIVE_NEGATION 0x00000008
|
|
#define NO_SEEK 0x00000010
|
|
#define LUN_CHECK 0x00000020
|
|
|
|
#define ENABLE_CE 0x01
|
|
#define DISABLE_CE 0x00
|
|
#define EEPROM_READ 0x80
|
|
|
|
/*
|
|
* The PCI configuration register offset for TRM_S1040
|
|
* Registers bit Definition
|
|
*/
|
|
#define TRMREG_ID 0x00 /* Vendor and Device ID */
|
|
#define TRMREG_COMMAND 0x04 /* PCI command register */
|
|
#define TRMREG_IOBASE 0x10 /* I/O Space base address */
|
|
#define TRMREG_ROMBASE 0x30 /* Expansion ROM Base Address */
|
|
#define TRMREG_INTLINE 0x3C /* Interrupt line */
|
|
|
|
/*
|
|
*
|
|
* The SCSI register offset for TRM_S1040
|
|
*
|
|
*/
|
|
#define TRMREG_SCSI_STATUS 0x80 /* SCSI Status (R) */
|
|
/* ######### */
|
|
#define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */
|
|
#define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */
|
|
#define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero*/
|
|
#define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */
|
|
#define COMMANDABORT 0x0040 /* SCSI command abort */
|
|
#define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */
|
|
#define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */
|
|
#define PARITYERROR 0x0008 /* SCSI parity error */
|
|
|
|
#define PHASEMASK 0x0007 /* Phase MSG/CD/IO */
|
|
#define PH_DATA_OUT 0x00 /* Data out phase */
|
|
#define PH_DATA_IN 0x01 /* Data in phase */
|
|
#define PH_COMMAND 0x02 /* Command phase */
|
|
#define PH_STATUS 0x03 /* Status phase */
|
|
#define PH_BUS_FREE 0x05 /* Invalid phase used as bus free */
|
|
#define PH_MSG_OUT 0x06 /* Message out phase */
|
|
#define PH_MSG_IN 0x07 /* Message in phase */
|
|
|
|
#define TRMREG_SCSI_CONTROL 0x80 /* SCSI Control (W) */
|
|
/* ######### */
|
|
#define DO_CLRATN 0x0400 /* Clear ATN */
|
|
#define DO_SETATN 0x0200 /* Set ATN */
|
|
#define DO_CMDABORT 0x0100 /* Abort SCSI command */
|
|
#define DO_RSTMODULE 0x0010 /* Reset SCSI chip */
|
|
#define DO_RSTSCSI 0x0008 /* Reset SCSI bus */
|
|
#define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */
|
|
#define DO_DATALATCH 0x0002 /* Enable SCSI bus data latch */
|
|
#define DO_HWRESELECT 0x0001 /* Enable hardware reselection */
|
|
#define TRMREG_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */
|
|
#define TRMREG_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */
|
|
#define TRMREG_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */
|
|
/* ######### */
|
|
#define INT_SCAM 0x80 /* SCAM selection interrupt */
|
|
#define INT_SELECT 0x40 /* Selection interrupt */
|
|
#define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */
|
|
#define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */
|
|
#define INT_RESELECTED 0x08 /* Reselected interrupt */
|
|
#define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt*/
|
|
#define INT_BUSSERVICE 0x02 /* Bus service interrupt */
|
|
#define INT_CMDDONE 0x01 /* SCSI command done interrupt */
|
|
#define TRMREG_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */
|
|
/*
|
|
* Bit Name Definition
|
|
* 07-05 0 RSVD Reversed. Always 0.
|
|
* 04 0 OFFSET4 Reversed for LVDS. Always 0.
|
|
* 03-00 0 OFFSET[03:00] Offset number from 0 to 15
|
|
*/
|
|
#define TRMREG_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W)*/
|
|
/* ######### */
|
|
#define LVDS_SYNC 0x20 /* Enable LVDS synchronous */
|
|
#define WIDE_SYNC 0x10 /* Enable WIDE synchronous */
|
|
#define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */
|
|
/*
|
|
* SYNCM 7 6 5 4 3 2 1 0
|
|
* Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0
|
|
* Default 0 0 0 0 0 0 0 0
|
|
*
|
|
*
|
|
* Bit Name Definition
|
|
* 07-06 0 RSVD Reversed. Always read 0
|
|
* 05 0 LVDS Reversed. Always read 0
|
|
* 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI transfer.
|
|
* 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode.
|
|
*
|
|
* @@ When this bit is set,
|
|
* the synchronous period bits 2:0
|
|
* in the Synchronous Mode register
|
|
* are used to transfer data
|
|
* at the Fast-20 rate.
|
|
* @@ When this bit is reset,
|
|
* the synchronous period bits 2:0
|
|
* in the Synchronous Mode Register
|
|
* are used to transfer data
|
|
* at the Fast-40 rate.
|
|
*
|
|
* 02-00 0 PERIOD[2:0]/SXPD[02:00] Synchronous SCSI Transfer Rate.
|
|
* These 3 bits specify
|
|
* the Synchronous SCSI Transfer Rate
|
|
* for Fast-20 and Fast-10.
|
|
* These bits are also reset
|
|
* by a SCSI Bus reset.
|
|
*
|
|
* For Fast-10 bit ALTPD = 0 and LVDS = 0
|
|
* and 0x00000004,0x00000002,0x00000001 is defined as follows :
|
|
*
|
|
* 000 100ns, 10.0 Mbytes/s
|
|
* 001 150ns, 6.6 Mbytes/s
|
|
* 010 200ns, 5.0 Mbytes/s
|
|
* 011 250ns, 4.0 Mbytes/s
|
|
* 100 300ns, 3.3 Mbytes/s
|
|
* 101 350ns, 2.8 Mbytes/s
|
|
* 110 400ns, 2.5 Mbytes/s
|
|
* 111 450ns, 2.2 Mbytes/s
|
|
*
|
|
* For Fast-20 bit ALTPD = 1 and LVDS = 0
|
|
* and 0x00000004,0x00000002,0x00000001 is defined as follows :
|
|
*
|
|
* 000 50ns, 20.0 Mbytes/s
|
|
* 001 75ns, 13.3 Mbytes/s
|
|
* 010 100ns, 10.0 Mbytes/s
|
|
* 011 125ns, 8.0 Mbytes/s
|
|
* 100 150ns, 6.6 Mbytes/s
|
|
* 101 175ns, 5.7 Mbytes/s
|
|
* 110 200ns, 5.0 Mbytes/s
|
|
* 111 250ns, 4.0 Mbytes/s
|
|
*
|
|
* For Fast-40 bit ALTPD = 0 and LVDS = 1
|
|
* and 0x00000004,0x00000002,0x00000001 is defined as follows :
|
|
*
|
|
* 000 25ns, 40.0 Mbytes/s
|
|
* 001 50ns, 20.0 Mbytes/s
|
|
* 010 75ns, 13.3 Mbytes/s
|
|
* 011 100ns, 10.0 Mbytes/s
|
|
* 100 125ns, 8.0 Mbytes/s
|
|
* 101 150ns, 6.6 Mbytes/s
|
|
* 110 175ns, 5.7 Mbytes/s
|
|
* 111 200ns, 5.0 Mbytes/s
|
|
*/
|
|
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W)*/
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */
|
|
/* ######### */
|
|
#define EN_SCAM 0x80 /* Enable SCAM selection interrupt*/
|
|
#define EN_SELECT 0x40 /* Enable selection interrupt */
|
|
#define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt*/
|
|
#define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt*/
|
|
#define EN_RESELECTED 0x08 /* Enable reselected interrupt */
|
|
#define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt*/
|
|
#define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */
|
|
#define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt*/
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */
|
|
/* ######### */
|
|
#define PHASELATCH 0x40 /* Enable phase latch */
|
|
#define INITIATOR 0x20 /* Enable initiator mode */
|
|
#define PARITYCHECK 0x10 /* Enable parity check */
|
|
#define BLOCKRST 0x01 /* Disable SCSI reset1 */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */
|
|
/* ######### */
|
|
#define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */
|
|
#define FILTER_DISABLE 0x08 /* Disable SCSI data filter */
|
|
#define ACTIVE_NEG 0x02 /* Enable active negation */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */
|
|
/* ######### */
|
|
#define SCMD_COMP 0x12 /* Command complete */
|
|
#define SCMD_SEL_ATN 0x60 /* Selection with ATN */
|
|
#define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */
|
|
#define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */
|
|
#define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */
|
|
#define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */
|
|
#define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */
|
|
#define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */
|
|
#define SCMD_MSGACCEPT 0xD8 /* Message accept */
|
|
/*
|
|
* Code Command Description
|
|
*
|
|
* 02 Enable reselection with FIFO
|
|
* 40 Select without ATN with FIFO
|
|
* 60 Select with ATN with FIFO
|
|
* 64 Select with ATN3 with FIFO
|
|
* A0 Select with ATN and stop with FIFO
|
|
* C0 Transfer information out with FIFO
|
|
* C1 Transfer information out with DMA
|
|
* C2 Transfer information in with FIFO
|
|
* C3 Transfer information in with DMA
|
|
* 12 Initiator command complete with FIFO
|
|
* 50 Initiator transfer information out sequence without ATN with FIFO
|
|
* 70 Initiator transfer information out sequence with ATN with FIFO
|
|
* 74 Initiator transfer information out sequence with ATN3 with FIFO
|
|
* 52 Initiator transfer information in sequence without ATN with FIFO
|
|
* 72 Initiator transfer information in sequence with ATN with FIFO
|
|
* 76 Initiator transfer information in sequence with ATN3 with FIFO
|
|
* 90 Initiator transfer information out command complete with FIFO
|
|
* 92 Initiator transfer information in command complete with FIFO
|
|
* D2 Enable selection
|
|
* 08 Reselection
|
|
* 48 Disconnect command with FIFO
|
|
* 88 Terminate command with FIFO
|
|
* C8 Target command complete with FIFO
|
|
* 18 SCAM Arbitration/ Selection
|
|
* 5A Enable reselection
|
|
* 98 Select without ATN with FIFO
|
|
* B8 Select with ATN with FIFO
|
|
* D8 Message Accepted
|
|
* 58 NOP
|
|
*/
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */
|
|
/* ######### */
|
|
#define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */
|
|
#define TCR0_SYNC_NEGO_DONE 0x4000 /* Synchronous nego done*/
|
|
#define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS synchronous*/
|
|
#define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE synchronous*/
|
|
#define TCR0_ENABLE_ALT 0x0800 /* Enable alternate synchronous */
|
|
#define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */
|
|
|
|
#define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */
|
|
#define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */
|
|
#define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */
|
|
#define TCR0_OFFSET_MASK 0x001F /* Offset number */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */
|
|
/* ######### */
|
|
#define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */
|
|
#define NON_TAG_BUSY 0x0080 /* Non tag command active */
|
|
#define ACTTAG_MASK 0x007F /* Active tags */
|
|
/*
|
|
*
|
|
* The DMA register offset for TRM_S1040
|
|
*
|
|
*/
|
|
#define TRMREG_DMA_COMMAND 0xA0 /* DMA Command (R/W) */
|
|
/* ######### */
|
|
#define XFERDATAIN 0x0103 /* Transfer data in */
|
|
#define XFERDATAOUT 0x0102 /* Transfer data out */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_DMA_CONTROL 0xA1 /* DMA Control (W) */
|
|
/* ######### */
|
|
#define STOPDMAXFER 0x08 /* Stop DMA transfer */
|
|
#define ABORTXFER 0x04 /* Abort DMA transfer */
|
|
#define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */
|
|
#define STARTDMAXFER 0x01 /* Start DMA transfer */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */
|
|
/* ######### */
|
|
#define XFERPENDING 0x80 /* Transfer pending */
|
|
#define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */
|
|
#define SCSICOMP 0x01 /* SCSI complete interrupt */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W)*/
|
|
/* ######### */
|
|
#define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */
|
|
/* ######### */
|
|
#define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W)*/
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */
|
|
|
|
/*
|
|
*
|
|
* The general register offset for TRM_S1040
|
|
*
|
|
*/
|
|
#define TRMREG_GEN_CONTROL 0xD4 /* Global Control */
|
|
/* ######### */
|
|
#define EN_EEPROM 0x10 /* Enable EEPROM programming */
|
|
#define AUTOTERM 0x04 /* Enable Auto SCSI terminator */
|
|
#define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */
|
|
#define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_GEN_STATUS 0xD5 /* Global Status */
|
|
/* ######### */
|
|
#define GTIMEOUT 0x80 /* Global timer reach 0 */
|
|
#define CON5068 0x10 /* External 50/68 pin connected */
|
|
#define CON68 0x08 /* Internal 68 pin connected */
|
|
#define CON50 0x04 /* Internal 50 pin connected */
|
|
#define WIDESCSI 0x02 /* Wide SCSI card */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */
|
|
/* ######### */
|
|
#define NVR_BITOUT 0x08 /* Serial data out */
|
|
#define NVR_BITIN 0x04 /* Serial data in */
|
|
#define NVR_CLOCK 0x02 /* Serial clock */
|
|
#define NVR_SELECT 0x01 /* Serial select */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_GEN_EDATA 0xD7 /* Parallel EEPROM data port */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */
|
|
/*
|
|
***************************************
|
|
*/
|
|
#define TRMREG_GEN_TIMER 0xDB /* Global timer */
|
|
|
|
/*
|
|
* The SEEPROM structure for TRM_S1040
|
|
*/
|
|
typedef struct NVRAM_TARGET_STRUCT
|
|
{
|
|
u_int8_t NvmTarCfg0; /* Target configuration byte 0 */
|
|
u_int8_t NvmTarPeriod; /* Target period */
|
|
u_int8_t NvmTarCfg2; /* Target configuration byte 2 */
|
|
u_int8_t NvmTarCfg3; /* Target configuration byte 3 */
|
|
} NVRAMTARGETTYPE;
|
|
/* NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode */
|
|
#define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */
|
|
#define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tag queuing */
|
|
#define NTC_DO_SEND_START 0x08 /* Send start command SPINUP*/
|
|
#define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */
|
|
#define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */
|
|
#define NTC_DO_PARITY_CHK 0x01 /* (it sould define at NAC )
|
|
Parity check enable */
|
|
|
|
/*
|
|
*
|
|
*
|
|
*
|
|
*/
|
|
typedef struct NVRAM_STRUC {
|
|
u_int8_t NvramSubVendorID[2]; /*0,1 Sub Vendor ID */
|
|
u_int8_t NvramSubSysID[2]; /*2,3 Sub System ID*/
|
|
u_int8_t NvramSubClass; /*4 Sub Class */
|
|
u_int8_t NvramVendorID[2]; /*5,6 Vendor ID */
|
|
u_int8_t NvramDeviceID[2]; /*7,8 Device ID */
|
|
u_int8_t NvramReserved; /*9 Reserved */
|
|
NVRAMTARGETTYPE NvramTarget[MAX_TARGETS];/* *10,11,12,13
|
|
*14,15,16,17 * ....
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* ....
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*70,71,72,73
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*/
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u_int8_t NvramScsiId; /*74 Host Adapter SCSI ID */
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u_int8_t NvramChannelCfg; /*75 Channel configuration */
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u_int8_t NvramDelayTime; /*76 Power on delay time */
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u_int8_t NvramMaxTag; /*77 Maximum tags */
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u_int8_t NvramReserved0; /*78 */
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u_int8_t NvramBootTarget; /*79 */
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u_int8_t NvramBootLun; /*80 */
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u_int8_t NvramReserved1; /*81 */
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u_int16_t Reserved[22]; /*82,..125 */
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|
u_int16_t NvramCheckSum; /*126,127*/
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|
} NVRAMTYPE,*PNVRAMTYPE;
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/* Nvram Initiater bits definition */
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|
#define MORE2_DRV 0x00000001
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|
#define GREATER_1G 0x00000002
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|
#define RST_SCSI_BUS 0x00000004
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|
#define ACTIVE_NEGATION 0x00000008
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|
#define NO_SEEK 0x00000010
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#define LUN_CHECK 0x00000020
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|
|
|
/* Nvram Adapter Cfg bits definition */
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|
#define NAC_SCANLUN 0x20 /* Include LUN as BIOS device*/
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|
#define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */
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|
#define NAC_GREATER_1G 0x02 /* > 1G support enable */
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|
#define NAC_GT2DRIVES 0x01 /* Support more than 2 drives*/
|
|
/*
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*#define NAC_DO_PARITY_CHK 0x08 // Parity check enable
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|
*/
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|
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#endif /* trm_H */
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