289 lines
7.6 KiB
C
289 lines
7.6 KiB
C
/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Local interrupt controller driver for Tegra SoCs.
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*/
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "pic_if.h"
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#define LIC_VIRQ_CPU 0x00
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#define LIC_VIRQ_COP 0x04
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#define LIC_VFRQ_CPU 0x08
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#define LIC_VFRQ_COP 0x0c
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#define LIC_ISR 0x10
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#define LIC_FIR 0x14
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#define LIC_FIR_SET 0x18
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#define LIC_FIR_CLR 0x1c
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#define LIC_CPU_IER 0x20
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#define LIC_CPU_IER_SET 0x24
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#define LIC_CPU_IER_CLR 0x28
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#define LIC_CPU_IEP_CLASS 0x2C
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#define LIC_COP_IER 0x30
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#define LIC_COP_IER_SET 0x34
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#define LIC_COP_IER_CLR 0x38
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#define LIC_COP_IEP_CLASS 0x3c
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#define WR4(_sc, _b, _r, _v) bus_write_4((_sc)->mem_res[_b], (_r), (_v))
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#define RD4(_sc, _b, _r) bus_read_4((_sc)->mem_res[_b], (_r))
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static struct resource_spec lic_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ SYS_RES_MEMORY, 2, RF_ACTIVE },
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{ SYS_RES_MEMORY, 3, RF_ACTIVE },
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{ SYS_RES_MEMORY, 4, RF_ACTIVE },
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{ -1, 0 }
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};
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static struct ofw_compat_data compat_data[] = {
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{"nvidia,tegra124-ictlr", 1},
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{"nvidia,tegra210-ictlr", 1},
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{NULL, 0}
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};
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struct tegra_lic_sc {
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device_t dev;
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struct resource *mem_res[nitems(lic_spec)];
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device_t parent;
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};
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static int
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tegra_lic_activate_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct tegra_lic_sc *sc = device_get_softc(dev);
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return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data));
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}
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static void
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tegra_lic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct tegra_lic_sc *sc = device_get_softc(dev);
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PIC_DISABLE_INTR(sc->parent, isrc);
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}
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static void
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tegra_lic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct tegra_lic_sc *sc = device_get_softc(dev);
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PIC_ENABLE_INTR(sc->parent, isrc);
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}
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static int
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tegra_lic_map_intr(device_t dev, struct intr_map_data *data,
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struct intr_irqsrc **isrcp)
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{
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struct tegra_lic_sc *sc = device_get_softc(dev);
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return (PIC_MAP_INTR(sc->parent, data, isrcp));
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}
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static int
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tegra_lic_deactivate_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct tegra_lic_sc *sc = device_get_softc(dev);
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return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data));
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}
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static int
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tegra_lic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct tegra_lic_sc *sc = device_get_softc(dev);
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return (PIC_SETUP_INTR(sc->parent, isrc, res, data));
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}
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static int
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tegra_lic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct tegra_lic_sc *sc = device_get_softc(dev);
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return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data));
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}
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static void
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tegra_lic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct tegra_lic_sc *sc = device_get_softc(dev);
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PIC_PRE_ITHREAD(sc->parent, isrc);
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}
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static void
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tegra_lic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct tegra_lic_sc *sc = device_get_softc(dev);
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PIC_POST_ITHREAD(sc->parent, isrc);
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}
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static void
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tegra_lic_post_filter(device_t dev, struct intr_irqsrc *isrc)
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{
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struct tegra_lic_sc *sc = device_get_softc(dev);
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PIC_POST_FILTER(sc->parent, isrc);
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}
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#ifdef SMP
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static int
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tegra_lic_bind_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct tegra_lic_sc *sc = device_get_softc(dev);
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return (PIC_BIND_INTR(sc->parent, isrc));
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}
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#endif
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static int
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tegra_lic_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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return (BUS_PROBE_DEFAULT);
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}
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static int
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tegra_lic_attach(device_t dev)
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{
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struct tegra_lic_sc *sc;
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phandle_t node;
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phandle_t parent_xref;
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int i, rv;
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sc = device_get_softc(dev);
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sc->dev = dev;
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node = ofw_bus_get_node(dev);
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rv = OF_getencprop(node, "interrupt-parent", &parent_xref,
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sizeof(parent_xref));
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if (rv <= 0) {
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device_printf(dev, "Cannot read parent node property\n");
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goto fail;
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}
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sc->parent = OF_device_from_xref(parent_xref);
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if (sc->parent == NULL) {
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device_printf(dev, "Cannott find parent controller\n");
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goto fail;
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}
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if (bus_alloc_resources(dev, lic_spec, sc->mem_res)) {
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device_printf(dev, "Cannott allocate resources\n");
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goto fail;
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}
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/* Disable all interrupts, route all to irq */
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for (i = 0; i < nitems(lic_spec); i++) {
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if (sc->mem_res[i] == NULL)
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continue;
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WR4(sc, i, LIC_CPU_IER_CLR, 0xFFFFFFFF);
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WR4(sc, i, LIC_CPU_IEP_CLASS, 0);
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}
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if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) {
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device_printf(dev, "Cannot register PIC\n");
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goto fail;
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}
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return (0);
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fail:
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bus_release_resources(dev, lic_spec, sc->mem_res);
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return (ENXIO);
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}
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static int
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tegra_lic_detach(device_t dev)
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{
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struct tegra_lic_sc *sc;
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int i;
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sc = device_get_softc(dev);
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for (i = 0; i < nitems(lic_spec); i++) {
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if (sc->mem_res[i] == NULL)
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continue;
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bus_release_resource(dev, SYS_RES_MEMORY, i,
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sc->mem_res[i]);
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}
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return (0);
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}
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static device_method_t tegra_lic_methods[] = {
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DEVMETHOD(device_probe, tegra_lic_probe),
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DEVMETHOD(device_attach, tegra_lic_attach),
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DEVMETHOD(device_detach, tegra_lic_detach),
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/* Interrupt controller interface */
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DEVMETHOD(pic_activate_intr, tegra_lic_activate_intr),
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DEVMETHOD(pic_disable_intr, tegra_lic_disable_intr),
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DEVMETHOD(pic_enable_intr, tegra_lic_enable_intr),
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DEVMETHOD(pic_map_intr, tegra_lic_map_intr),
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DEVMETHOD(pic_deactivate_intr, tegra_lic_deactivate_intr),
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DEVMETHOD(pic_setup_intr, tegra_lic_setup_intr),
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DEVMETHOD(pic_teardown_intr, tegra_lic_teardown_intr),
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DEVMETHOD(pic_pre_ithread, tegra_lic_pre_ithread),
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DEVMETHOD(pic_post_ithread, tegra_lic_post_ithread),
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DEVMETHOD(pic_post_filter, tegra_lic_post_filter),
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#ifdef SMP
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DEVMETHOD(pic_bind_intr, tegra_lic_bind_intr),
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#endif
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DEVMETHOD_END
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};
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devclass_t tegra_lic_devclass;
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static DEFINE_CLASS_0(lic, tegra_lic_driver, tegra_lic_methods,
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sizeof(struct tegra_lic_sc));
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EARLY_DRIVER_MODULE(tegra_lic, simplebus, tegra_lic_driver, tegra_lic_devclass,
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NULL, NULL, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE + 1);
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