Robert Watson 9725389e1e Don't conditionally define CACHE_LINE_SHIFT, as we anticipate sizing ... a fair number of static data structures, making this an unlikely option to try to change without also changing source code. [1] Change default cache line size on ia64, sparc64, and sun4v to 128 bytes, as this was what rtld-elf was already using on those platforms. [2] Suggested by: bde [1], jhb [2] MFC after: 2 weeks		2009-04-20 12:59:23 +00:00
..
_bus.h
_inttypes.h
_limits.h
_stdint.h
_types.h
asi.h	For cheetah-class CPUs ensure that the dt512_0 is set to hold 8k pages	2008-09-08 21:24:25 +00:00
asm.h
asmacros.h
atomic.h	- bump __FreeBSD version to reflect added buf_ring, memory barriers,	2008-11-22 05:55:56 +00:00
bus_common.h
bus_dma.h
bus_private.h	Improve r185008 so the streaming cache is only flushed when	2009-02-10 21:51:33 +00:00
bus.h
cache.h	- USIII-based machines can consist of CPUs having different cache	2008-09-02 21:13:54 +00:00
ccr.h
clock.h	- USIII-based machines can consist of CPUs running at different	2008-09-03 17:39:19 +00:00
cpu.h	Flesh out MMU and cache handling of cheetah-class CPUs.	2008-09-04 19:58:52 +00:00
cpufunc.h	- USIII-based machines can consist of CPUs running at different	2008-09-03 17:39:19 +00:00
db_machdep.h
dcr.h	Flesh out MMU and cache handling of cheetah-class CPUs.	2008-09-04 19:58:52 +00:00
elf.h	Add AT_EXECPATH ELF auxinfo entry type. The value's a_ptr is a pointer	2009-03-17 12:50:16 +00:00
endian.h
exec.h
float.h
floatingpoint.h
fp.h
frame.h
fsr.h
gdb_machdep.h
idprom.h
ieee.h
ieeefp.h
in_cksum.h
instr.h
intr_machdep.h	Use the interrupt level right below PIL_FAST for executing interrupt	2008-11-19 22:12:32 +00:00
iommureg.h	- Allow the front-end to specify that iommu(4) should disable	2008-11-16 19:53:49 +00:00
iommuvar.h	- Allow the front-end to specify that iommu(4) should disable	2008-11-16 19:53:49 +00:00
kdb.h
kerneldump.h
ktr.h
limits.h
lsu.h
md_var.h
memdev.h
metadata.h
mutex.h
ofw_machdep.h	Modularize the Open Firmware client interface to allow run-time switching	2008-12-20 00:33:10 +00:00
ofw_mem.h
ofw_nexus.h
param.h	Don't conditionally define CACHE_LINE_SHIFT, as we anticipate sizing	2009-04-20 12:59:23 +00:00
pcb.h
pcpu.h	- USIII-based machines can consist of CPUs running at different	2008-09-03 17:39:19 +00:00
pmap.h
pmc_mdep.h
proc.h
profile.h
pstate.h
ptrace.h
reg.h
reloc.h
resource.h
runq.h
sc_machdep.h
setjmp.h
sf_buf.h
sigframe.h
signal.h
smp.h	- Newer firmware versions no longer provide SUNW,stop-self so just	2008-09-18 13:56:30 +00:00
stack.h
stdarg.h
sysarch.h
tick.h	Use the STICK timers only when absolutely necessary, i.e. if a machine	2008-09-20 11:26:13 +00:00
tlb.h	- Currently the PMAP code is laid out to let the kernel TSB cover the	2009-01-01 14:01:21 +00:00
trap.h	- There's no need to wrap kdb_active and kdb_trap() in #ifdef KDB as	2009-03-19 20:46:51 +00:00
tsb.h
tstate.h
tte.h	The physical address space of cheetah-class CPUs has been extended	2008-09-04 19:43:14 +00:00
ucontext.h
upa.h
utrap.h
varargs.h
ver.h	- USIII-based machines can consist of CPUs running at different	2008-09-03 17:39:19 +00:00
vmparam.h	- Use the generally more appropriate PROM base rather than the	2009-02-10 21:48:42 +00:00
watch.h
wstate.h