6fc729af63
It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
205 lines
7.9 KiB
C
205 lines
7.9 KiB
C
/* $NetBSD: frame.h,v 1.6 2003/10/05 19:44:58 matt Exp $ */
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/*
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* Copyright (c) 1994-1997 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ASMACROS_H_
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#define _MACHINE_ASMACROS_H_
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#ifdef _KERNEL
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#ifdef LOCORE
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/*
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* ASM macros for pushing and pulling trapframes from the stack
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*
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* These macros are used to handle the irqframe and trapframe structures
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* defined above.
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*/
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/*
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* PUSHFRAME - macro to push a trap frame on the stack in the current mode
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* Since the current mode is used, the SVC lr field is not defined.
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*
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* NOTE: r13 and r14 are stored separately as a work around for the
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* SA110 rev 2 STM^ bug
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*/
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#define PUSHFRAME \
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str lr, [sp, #-4]!; /* Push the return address */ \
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sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
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stmia sp, {r0-r12}; /* Push the user mode registers */ \
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add r0, sp, #(4*13); /* Adjust the stack pointer */ \
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stmia r0, {r13-r14}^; /* Push the user mode registers */ \
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mov r0, r0; /* NOP for previous instruction */ \
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mrs r0, spsr_all; /* Put the SPSR on the stack */ \
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str r0, [sp, #-4]!;
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/*
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* PULLFRAME - macro to pull a trap frame from the stack in the current mode
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* Since the current mode is used, the SVC lr field is ignored.
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*/
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#define PULLFRAME \
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ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
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msr spsr_all, r0; \
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ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
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mov r0, r0; /* NOP for previous instruction */ \
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add sp, sp, #(4*17); /* Adjust the stack pointer */ \
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ldr lr, [sp], #0x0004; /* Pull the return address */
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/*
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* PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
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* This should only be used if the processor is not currently in SVC32
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* mode. The processor mode is switched to SVC mode and the trap frame is
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* stored. The SVC lr field is used to store the previous value of
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* lr in SVC mode.
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*
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* NOTE: r13 and r14 are stored separately as a work around for the
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* SA110 rev 2 STM^ bug
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*/
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#define PUSHFRAMEINSVC \
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stmdb sp, {r0-r3}; /* Save 4 registers */ \
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mov r0, lr; /* Save xxx32 r14 */ \
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mov r1, sp; /* Save xxx32 sp */ \
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mrs r3, spsr; /* Save xxx32 spsr */ \
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mrs r2, cpsr; /* Get the CPSR */ \
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bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \
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orr r2, r2, #(PSR_SVC32_MODE); \
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msr cpsr_c, r2; /* Punch into SVC mode */ \
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mov r2, sp; /* Save SVC sp */ \
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str r0, [sp, #-4]!; /* Push return address */ \
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str lr, [sp, #-4]!; /* Push SVC lr */ \
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str r2, [sp, #-4]!; /* Push SVC sp */ \
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msr spsr_all, r3; /* Restore correct spsr */ \
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ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \
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sub sp, sp, #(4*15); /* Adjust the stack pointer */ \
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stmia sp, {r0-r12}; /* Push the user mode registers */ \
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add r0, sp, #(4*13); /* Adjust the stack pointer */ \
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stmia r0, {r13-r14}^; /* Push the user mode registers */ \
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mov r0, r0; /* NOP for previous instruction */ \
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mrs r0, spsr_all; /* Put the SPSR on the stack */ \
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str r0, [sp, #-4]!
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/*
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* PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack
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* in SVC32 mode and restore the saved processor mode and PC.
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* This should be used when the SVC lr register needs to be restored on
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* exit.
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*/
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#define PULLFRAMEFROMSVCANDEXIT \
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ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
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msr spsr_all, r0; /* restore SPSR */ \
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ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
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mov r0, r0; /* NOP for previous instruction */ \
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add sp, sp, #(4*15); /* Adjust the stack pointer */ \
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ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */
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#define DATA(name) \
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.data ; \
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_ALIGN_DATA ; \
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.globl name ; \
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.type name, %object ; \
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name:
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#define EMPTY
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#define GET_CURPCB_ENTER \
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ldr r1, .Laflt_curpcb ;\
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ldr r1, [r1]
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/*
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* This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at
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* the top of interrupt/exception handlers.
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*
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* When invoked, r0 *must* contain the value of SPSR on the current
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* trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS
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* is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME.
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*/
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#define ENABLE_ALIGNMENT_FAULTS \
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and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\
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teq r0, #(PSR_USR32_MODE) ;\
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bne 1f /* Not USR mode skip AFLT */ ;\
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GET_CURPCB_ENTER /* r1 = curpcb */ ;\
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cmp r1, #0x00 /* curpcb NULL? */ ;\
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ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\
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tstne r1, #PCB_NOALIGNFLT ;\
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beq 1f /* AFLTs already enabled */ ;\
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ldr r2, .Laflt_cpufuncs ;\
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mov lr, pc ;\
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ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\
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1:
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#define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \
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ldr r0, [sp] /* Get the SPSR from stack */ ;\
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mrs r4, cpsr /* save CPSR */ ;\
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and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\
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teq r0, #(PSR_USR32_MODE) ;\
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bne 2f /* Nope, get out now */ ;\
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bic r4, r4, #(I32_bit) ;\
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1: orr r0, r4, #(I32_bit) /* Disable IRQs */ ;\
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msr cpsr_c, r0 ;\
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ldr r5, .Laflt_curthread ;\
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ldr r5, [r5] ;\
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ldr r5, [r5, #(TD_FLAGS)] ;\
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and r5, r5, #(TDF_ASTPENDING) ;\
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teq r5, #0x00000000 ;\
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beq 2f /* Nope. Just bail */ ;\
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msr cpsr_c, r4 /* Restore interrupts */ ;\
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mov r0, sp ;\
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adr lr, 1b ;\
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b _C_LABEL(ast) /* ast(frame) */ ;\
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2:
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#define AST_ALIGNMENT_FAULT_LOCALS ;\
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.Laflt_curpcb: ;\
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.word _C_LABEL(__pcpu) + PC_CURPCB ;\
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.Laflt_cpufuncs: ;\
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.word _C_LABEL(cpufuncs) ;\
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.Laflt_curthread: ;\
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.word _C_LABEL(__pcpu) + PC_CURTHREAD
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#endif /* LOCORE */
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#endif /* _KERNEL */
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#endif /* !_MACHINE_ASMACROS_H_ */
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