04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
140 lines
4.4 KiB
C
140 lines
4.4 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Interface to Core, IO and DDR Clock.
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*
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* <hr>$Revision: 45089 $<hr>
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*/
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#ifndef __CVMX_CLOCK_H__
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#define __CVMX_CLOCK_H__
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-lmcx-defs.h>
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#else
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#include "cvmx.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Enumeration of different Clocks in Octeon.
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*/
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typedef enum{
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CVMX_CLOCK_RCLK, /**< Clock used by cores, coherent bus and L2 cache. */
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CVMX_CLOCK_SCLK, /**< Clock used by IO blocks. */
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CVMX_CLOCK_DDR, /**< Clock used by DRAM */
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CVMX_CLOCK_CORE, /**< Alias for CVMX_CLOCK_RCLK */
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CVMX_CLOCK_TIM, /**< Alias for CVMX_CLOCK_SCLK */
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CVMX_CLOCK_IPD, /**< Alias for CVMX_CLOCK_SCLK */
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} cvmx_clock_t;
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/**
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* Get cycle count based on the clock type.
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*
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* @param clock - Enumeration of the clock type.
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* @return - Get the number of cycles executed so far.
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*/
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static inline uint64_t cvmx_clock_get_count(cvmx_clock_t clock)
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{
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switch(clock)
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{
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case CVMX_CLOCK_RCLK:
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case CVMX_CLOCK_CORE:
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{
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#ifndef __mips__
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return cvmx_read_csr(CVMX_IPD_CLK_COUNT);
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#elif defined(CVMX_ABI_O32)
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uint32_t tmp_low, tmp_hi;
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asm volatile (
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" .set push \n"
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" .set mips64r2 \n"
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" .set noreorder \n"
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" rdhwr %[tmpl], $31 \n"
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" dsrl %[tmph], %[tmpl], 32 \n"
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" sll %[tmpl], 0 \n"
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" sll %[tmph], 0 \n"
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" .set pop \n"
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: [tmpl] "=&r" (tmp_low), [tmph] "=&r" (tmp_hi) : );
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return(((uint64_t)tmp_hi << 32) + tmp_low);
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#else
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uint64_t cycle;
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CVMX_RDHWR(cycle, 31);
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return(cycle);
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#endif
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}
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case CVMX_CLOCK_SCLK:
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case CVMX_CLOCK_TIM:
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case CVMX_CLOCK_IPD:
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return cvmx_read_csr(CVMX_IPD_CLK_COUNT);
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case CVMX_CLOCK_DDR:
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
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return cvmx_read_csr(CVMX_LMCX_DCLK_CNT(0));
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else
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return ((cvmx_read_csr(CVMX_LMCX_DCLK_CNT_HI(0)) << 32) | cvmx_read_csr(CVMX_LMCX_DCLK_CNT_LO(0)));
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}
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cvmx_dprintf("cvmx_clock_get_count: Unknown clock type\n");
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return 0;
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}
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extern uint64_t cvmx_clock_get_rate(cvmx_clock_t clock);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CVMX_CLOCK_H__ */
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