04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
675 lines
22 KiB
C
675 lines
22 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* This file provides bootbus flash operations
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*
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* <hr>$Revision: 49448 $<hr>
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*
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*
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*/
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#include "cvmx-config.h"
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#include "cvmx.h"
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#include "cvmx-sysinfo.h"
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#include "cvmx-spinlock.h"
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#include "cvmx-flash.h"
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#define MAX_NUM_FLASH_CHIPS 8 /* Maximum number of flash chips */
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#define MAX_NUM_REGIONS 8 /* Maximum number of block regions per chip */
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#define DEBUG 1
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#define CFI_CMDSET_NONE 0
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#define CFI_CMDSET_INTEL_EXTENDED 1
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#define CFI_CMDSET_AMD_STANDARD 2
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#define CFI_CMDSET_INTEL_STANDARD 3
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#define CFI_CMDSET_AMD_EXTENDED 4
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#define CFI_CMDSET_MITSU_STANDARD 256
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#define CFI_CMDSET_MITSU_EXTENDED 257
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#define CFI_CMDSET_SST 258
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typedef struct
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{
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void * base_ptr; /**< Memory pointer to start of flash */
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int is_16bit; /**< Chip is 16bits wide in 8bit mode */
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uint16_t vendor; /**< Vendor ID of Chip */
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int size; /**< Size of the chip in bytes */
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uint64_t erase_timeout; /**< Erase timeout in cycles */
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uint64_t write_timeout; /**< Write timeout in cycles */
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int num_regions; /**< Number of block regions */
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cvmx_flash_region_t region[MAX_NUM_REGIONS];
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} cvmx_flash_t;
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static CVMX_SHARED cvmx_flash_t flash_info[MAX_NUM_FLASH_CHIPS];
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static CVMX_SHARED cvmx_spinlock_t flash_lock = CVMX_SPINLOCK_UNLOCKED_INITIALIZER;
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/**
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* @INTERNAL
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* Read a byte from flash
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*
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* @param chip_id Chip to read from
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* @param offset Offset into the chip
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* @return Value read
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*/
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static uint8_t __cvmx_flash_read8(int chip_id, int offset)
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{
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return *(volatile uint8_t *)(flash_info[chip_id].base_ptr + offset);
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}
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/**
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* @INTERNAL
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* Read a byte from flash (for commands)
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*
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* @param chip_id Chip to read from
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* @param offset Offset into the chip
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* @return Value read
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*/
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static uint8_t __cvmx_flash_read_cmd(int chip_id, int offset)
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{
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if (flash_info[chip_id].is_16bit)
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offset<<=1;
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return __cvmx_flash_read8(chip_id, offset);
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}
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/**
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* @INTERNAL
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* Read 16bits from flash (for commands)
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*
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* @param chip_id Chip to read from
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* @param offset Offset into the chip
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* @return Value read
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*/
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static uint16_t __cvmx_flash_read_cmd16(int chip_id, int offset)
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{
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uint16_t v = __cvmx_flash_read_cmd(chip_id, offset);
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v |= __cvmx_flash_read_cmd(chip_id, offset + 1)<<8;
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return v;
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}
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/**
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* @INTERNAL
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* Write a byte to flash
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*
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* @param chip_id Chip to write to
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* @param offset Offset into the chip
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* @param data Value to write
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*/
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static void __cvmx_flash_write8(int chip_id, int offset, uint8_t data)
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{
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volatile uint8_t *flash_ptr = (volatile uint8_t *)flash_info[chip_id].base_ptr;
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flash_ptr[offset] = data;
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}
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/**
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* @INTERNAL
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* Write a byte to flash (for commands)
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*
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* @param chip_id Chip to write to
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* @param offset Offset into the chip
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* @param data Value to write
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*/
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static void __cvmx_flash_write_cmd(int chip_id, int offset, uint8_t data)
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{
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volatile uint8_t *flash_ptr = (volatile uint8_t *)flash_info[chip_id].base_ptr;
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flash_ptr[offset<<flash_info[chip_id].is_16bit] = data;
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}
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/**
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* @INTERNAL
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* Query a address and see if a CFI flash chip is there.
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*
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* @param chip_id Chip ID data to fill in if the chip is there
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* @param base_ptr Memory pointer to the start address to query
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* @return Zero on success, Negative on failure
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*/
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static int __cvmx_flash_queury_cfi(int chip_id, void *base_ptr)
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{
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int region;
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cvmx_flash_t *flash = flash_info + chip_id;
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/* Set the minimum needed for the read and write primitives to work */
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flash->base_ptr = base_ptr;
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flash->is_16bit = 1; /* FIXME: Currently assumes the chip is 16bits */
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/* Put flash in CFI query mode */
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__cvmx_flash_write_cmd(chip_id, 0x00, 0xf0); /* Reset the flash chip */
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__cvmx_flash_write_cmd(chip_id, 0x55, 0x98);
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/* Make sure we get the QRY response we should */
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if ((__cvmx_flash_read_cmd(chip_id, 0x10) != 'Q') ||
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(__cvmx_flash_read_cmd(chip_id, 0x11) != 'R') ||
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(__cvmx_flash_read_cmd(chip_id, 0x12) != 'Y'))
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{
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flash->base_ptr = NULL;
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return -1;
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}
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/* Read the 16bit vendor ID */
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flash->vendor = __cvmx_flash_read_cmd16(chip_id, 0x13);
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/* Read the write timeout. The timeout is microseconds(us) is 2^0x1f
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typically. The worst case is this value time 2^0x23 */
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flash->write_timeout = 1ull << (__cvmx_flash_read_cmd(chip_id, 0x1f) +
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__cvmx_flash_read_cmd(chip_id, 0x23));
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/* Read the erase timeout. The timeout is milliseconds(ms) is 2^0x21
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typically. The worst case is this value time 2^0x25 */
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flash->erase_timeout = 1ull << (__cvmx_flash_read_cmd(chip_id, 0x21) +
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__cvmx_flash_read_cmd(chip_id, 0x25));
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/* Get the flash size. This is 2^0x27 */
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flash->size = 1<<__cvmx_flash_read_cmd(chip_id, 0x27);
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/* Get the number of different sized block regions from 0x2c */
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flash->num_regions = __cvmx_flash_read_cmd(chip_id, 0x2c);
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int start_offset = 0;
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/* Loop through all regions get information about each */
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for (region=0; region<flash->num_regions; region++)
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{
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cvmx_flash_region_t *rgn_ptr = flash->region + region;
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rgn_ptr->start_offset = start_offset;
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/* The number of blocks in each region is a 16 bit little endian
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endian field. It is encoded at 0x2d + region*4 as (blocks-1) */
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uint16_t blocks = __cvmx_flash_read_cmd16(chip_id, 0x2d + region*4);
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rgn_ptr->num_blocks = 1u + blocks;
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/* The size of each block is a 16 bit little endian endian field. It
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is encoded at 0x2d + region*4 + 2 as (size/256). Zero is a special
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case representing 128 */
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uint16_t size = __cvmx_flash_read_cmd16(chip_id, 0x2d + region*4 + 2);
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if (size == 0)
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rgn_ptr->block_size = 128;
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else
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rgn_ptr->block_size = 256u * size;
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start_offset += rgn_ptr->block_size * rgn_ptr->num_blocks;
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}
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/* Take the chip out of CFI query mode */
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switch (flash_info[chip_id].vendor)
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{
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case CFI_CMDSET_AMD_STANDARD:
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__cvmx_flash_write_cmd(chip_id, 0x00, 0xf0);
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case CFI_CMDSET_INTEL_STANDARD:
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case CFI_CMDSET_INTEL_EXTENDED:
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__cvmx_flash_write_cmd(chip_id, 0x00, 0xff);
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break;
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}
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/* Convert the timeouts to cycles */
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flash->write_timeout *= cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000000;
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flash->erase_timeout *= cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000;
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#if DEBUG
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/* Print the information about the chip */
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cvmx_dprintf("cvmx-flash: Base pointer: %p\n"
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" Vendor: 0x%04x\n"
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" Size: %d bytes\n"
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" Num regions: %d\n"
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" Erase timeout: %llu cycles\n"
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" Write timeout: %llu cycles\n",
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flash->base_ptr,
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(unsigned int)flash->vendor,
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flash->size,
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flash->num_regions,
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(unsigned long long)flash->erase_timeout,
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(unsigned long long)flash->write_timeout);
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for (region=0; region<flash->num_regions; region++)
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{
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cvmx_dprintf(" Region %d: offset 0x%x, %d blocks, %d bytes/block\n",
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region,
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flash->region[region].start_offset,
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flash->region[region].num_blocks,
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flash->region[region].block_size);
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}
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#endif
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return 0;
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}
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/**
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* Initialize the flash access library
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*/
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void cvmx_flash_initialize(void)
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{
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int boot_region;
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int chip_id = 0;
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memset(flash_info, 0, sizeof(flash_info));
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/* Loop through each boot bus chip select region */
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for (boot_region=0; boot_region<MAX_NUM_FLASH_CHIPS; boot_region++)
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{
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cvmx_mio_boot_reg_cfgx_t region_cfg;
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region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFG0 + boot_region*8);
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/* Only try chip select regions that are enabled. This assumes the
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bootloader already setup the flash */
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if (region_cfg.s.en)
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{
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/* Convert the hardware address to a pointer. Note that the bootbus,
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unlike memory, isn't 1:1 mapped in the simple exec */
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void *base_ptr = cvmx_phys_to_ptr((region_cfg.s.base<<16) | 0xffffffff80000000ull);
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if (__cvmx_flash_queury_cfi(chip_id, base_ptr) == 0)
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{
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/* Valid CFI flash chip found */
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chip_id++;
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}
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}
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}
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if (chip_id == 0)
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cvmx_dprintf("cvmx-flash: No CFI chips found\n");
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}
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/**
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* Return a pointer to the flash chip
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*
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* @param chip_id Chip ID to return
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* @return NULL if the chip doesn't exist
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*/
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void *cvmx_flash_get_base(int chip_id)
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{
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return flash_info[chip_id].base_ptr;
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}
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/**
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* Return the number of erasable regions on the chip
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*
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* @param chip_id Chip to return info for
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* @return Number of regions
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*/
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int cvmx_flash_get_num_regions(int chip_id)
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{
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return flash_info[chip_id].num_regions;
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}
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/**
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* Return information about a flash chips region
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*
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* @param chip_id Chip to get info for
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* @param region Region to get info for
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* @return Region information
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*/
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const cvmx_flash_region_t *cvmx_flash_get_region_info(int chip_id, int region)
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{
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return flash_info[chip_id].region + region;
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}
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/**
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* Erase a block on the flash chip
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*
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* @param chip_id Chip to erase a block on
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* @param region Region to erase a block in
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* @param block Block number to erase
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* @return Zero on success. Negative on failure
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*/
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int cvmx_flash_erase_block(int chip_id, int region, int block)
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{
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cvmx_spinlock_lock(&flash_lock);
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#if DEBUG
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cvmx_dprintf("cvmx-flash: Erasing chip %d, region %d, block %d\n",
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chip_id, region, block);
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#endif
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int offset = flash_info[chip_id].region[region].start_offset +
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block * flash_info[chip_id].region[region].block_size;
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switch (flash_info[chip_id].vendor)
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{
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case CFI_CMDSET_AMD_STANDARD:
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{
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/* Send the erase sector command sequence */
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__cvmx_flash_write_cmd(chip_id, 0x00, 0xf0); /* Reset the flash chip */
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__cvmx_flash_write_cmd(chip_id, 0x555, 0xaa);
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__cvmx_flash_write_cmd(chip_id, 0x2aa, 0x55);
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__cvmx_flash_write_cmd(chip_id, 0x555, 0x80);
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__cvmx_flash_write_cmd(chip_id, 0x555, 0xaa);
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__cvmx_flash_write_cmd(chip_id, 0x2aa, 0x55);
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__cvmx_flash_write8(chip_id, offset, 0x30);
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/* Loop checking status */
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uint8_t status = __cvmx_flash_read8(chip_id, offset);
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uint64_t start_cycle = cvmx_get_cycle();
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while (1)
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{
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/* Read the status and xor it with the old status so we can
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find toggling bits */
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uint8_t old_status = status;
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status = __cvmx_flash_read8(chip_id, offset);
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uint8_t toggle = status ^ old_status;
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/* Check if the erase in progress bit is toggling */
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if (toggle & (1<<6))
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{
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/* Check hardware timeout */
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if (status & (1<<5))
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{
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/* Chip has signalled a timeout. Reread the status */
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old_status = __cvmx_flash_read8(chip_id, offset);
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status = __cvmx_flash_read8(chip_id, offset);
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toggle = status ^ old_status;
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/* Check if the erase in progress bit is toggling */
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if (toggle & (1<<6))
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{
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cvmx_dprintf("cvmx-flash: Hardware timeout erasing block\n");
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cvmx_spinlock_unlock(&flash_lock);
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return -1;
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}
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else
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break; /* Not toggling, erase complete */
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}
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}
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else
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break; /* Not toggling, erase complete */
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if (cvmx_get_cycle() > start_cycle + flash_info[chip_id].erase_timeout)
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{
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cvmx_dprintf("cvmx-flash: Timeout erasing block\n");
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cvmx_spinlock_unlock(&flash_lock);
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return -1;
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}
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}
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__cvmx_flash_write_cmd(chip_id, 0x00, 0xf0); /* Reset the flash chip */
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cvmx_spinlock_unlock(&flash_lock);
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return 0;
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}
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case CFI_CMDSET_INTEL_STANDARD:
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case CFI_CMDSET_INTEL_EXTENDED:
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{
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/* Send the erase sector command sequence */
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__cvmx_flash_write_cmd(chip_id, 0x00, 0xff); /* Reset the flash chip */
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__cvmx_flash_write8(chip_id, offset, 0x20);
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__cvmx_flash_write8(chip_id, offset, 0xd0);
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/* Loop checking status */
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uint8_t status = __cvmx_flash_read8(chip_id, offset);
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uint64_t start_cycle = cvmx_get_cycle();
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while ((status & 0x80) == 0)
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{
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if (cvmx_get_cycle() > start_cycle + flash_info[chip_id].erase_timeout)
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{
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cvmx_dprintf("cvmx-flash: Timeout erasing block\n");
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cvmx_spinlock_unlock(&flash_lock);
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return -1;
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}
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status = __cvmx_flash_read8(chip_id, offset);
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}
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/* Check the final status */
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if (status & 0x7f)
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{
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cvmx_dprintf("cvmx-flash: Hardware failure erasing block\n");
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cvmx_spinlock_unlock(&flash_lock);
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return -1;
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}
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__cvmx_flash_write_cmd(chip_id, 0x00, 0xff); /* Reset the flash chip */
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cvmx_spinlock_unlock(&flash_lock);
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return 0;
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}
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}
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cvmx_dprintf("cvmx-flash: Unsupported flash vendor\n");
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cvmx_spinlock_unlock(&flash_lock);
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return -1;
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}
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/**
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* Write a block on the flash chip
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*
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* @param chip_id Chip to write a block on
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* @param region Region to write a block in
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* @param block Block number to write
|
|
* @param data Data to write
|
|
* @return Zero on success. Negative on failure
|
|
*/
|
|
int cvmx_flash_write_block(int chip_id, int region, int block, const void *data)
|
|
{
|
|
cvmx_spinlock_lock(&flash_lock);
|
|
#if DEBUG
|
|
cvmx_dprintf("cvmx-flash: Writing chip %d, region %d, block %d\n",
|
|
chip_id, region, block);
|
|
#endif
|
|
int offset = flash_info[chip_id].region[region].start_offset +
|
|
block * flash_info[chip_id].region[region].block_size;
|
|
int len = flash_info[chip_id].region[region].block_size;
|
|
const uint8_t *ptr = (const uint8_t *)data;
|
|
|
|
switch (flash_info[chip_id].vendor)
|
|
{
|
|
case CFI_CMDSET_AMD_STANDARD:
|
|
{
|
|
/* Loop through one byte at a time */
|
|
while (len--)
|
|
{
|
|
/* Send the program sequence */
|
|
__cvmx_flash_write_cmd(chip_id, 0x00, 0xf0); /* Reset the flash chip */
|
|
__cvmx_flash_write_cmd(chip_id, 0x555, 0xaa);
|
|
__cvmx_flash_write_cmd(chip_id, 0x2aa, 0x55);
|
|
__cvmx_flash_write_cmd(chip_id, 0x555, 0xa0);
|
|
__cvmx_flash_write8(chip_id, offset, *ptr);
|
|
|
|
/* Loop polling for status */
|
|
uint64_t start_cycle = cvmx_get_cycle();
|
|
while (1)
|
|
{
|
|
uint8_t status = __cvmx_flash_read8(chip_id, offset);
|
|
if (((status ^ *ptr) & (1<<7)) == 0)
|
|
break; /* Data matches, this byte is done */
|
|
else if (status & (1<<5))
|
|
{
|
|
/* Hardware timeout, recheck status */
|
|
status = __cvmx_flash_read8(chip_id, offset);
|
|
if (((status ^ *ptr) & (1<<7)) == 0)
|
|
break; /* Data matches, this byte is done */
|
|
else
|
|
{
|
|
cvmx_dprintf("cvmx-flash: Hardware write timeout\n");
|
|
cvmx_spinlock_unlock(&flash_lock);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
if (cvmx_get_cycle() > start_cycle + flash_info[chip_id].write_timeout)
|
|
{
|
|
cvmx_dprintf("cvmx-flash: Timeout writing block\n");
|
|
cvmx_spinlock_unlock(&flash_lock);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
/* Increment to the next byte */
|
|
ptr++;
|
|
offset++;
|
|
}
|
|
|
|
__cvmx_flash_write_cmd(chip_id, 0x00, 0xf0); /* Reset the flash chip */
|
|
cvmx_spinlock_unlock(&flash_lock);
|
|
return 0;
|
|
}
|
|
case CFI_CMDSET_INTEL_STANDARD:
|
|
case CFI_CMDSET_INTEL_EXTENDED:
|
|
{
|
|
cvmx_dprintf("%s:%d len=%d\n", __FUNCTION__, __LINE__, len);
|
|
/* Loop through one byte at a time */
|
|
while (len--)
|
|
{
|
|
/* Send the program sequence */
|
|
__cvmx_flash_write_cmd(chip_id, 0x00, 0xff); /* Reset the flash chip */
|
|
__cvmx_flash_write8(chip_id, offset, 0x40);
|
|
__cvmx_flash_write8(chip_id, offset, *ptr);
|
|
|
|
/* Loop polling for status */
|
|
uint8_t status = __cvmx_flash_read8(chip_id, offset);
|
|
uint64_t start_cycle = cvmx_get_cycle();
|
|
while ((status & 0x80) == 0)
|
|
{
|
|
if (cvmx_get_cycle() > start_cycle + flash_info[chip_id].write_timeout)
|
|
{
|
|
cvmx_dprintf("cvmx-flash: Timeout writing block\n");
|
|
cvmx_spinlock_unlock(&flash_lock);
|
|
return -1;
|
|
}
|
|
status = __cvmx_flash_read8(chip_id, offset);
|
|
}
|
|
|
|
/* Check the final status */
|
|
if (status & 0x7f)
|
|
{
|
|
cvmx_dprintf("cvmx-flash: Hardware failure erasing block\n");
|
|
cvmx_spinlock_unlock(&flash_lock);
|
|
return -1;
|
|
}
|
|
|
|
/* Increment to the next byte */
|
|
ptr++;
|
|
offset++;
|
|
}
|
|
cvmx_dprintf("%s:%d\n", __FUNCTION__, __LINE__);
|
|
|
|
__cvmx_flash_write_cmd(chip_id, 0x00, 0xff); /* Reset the flash chip */
|
|
cvmx_spinlock_unlock(&flash_lock);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
cvmx_dprintf("cvmx-flash: Unsupported flash vendor\n");
|
|
cvmx_spinlock_unlock(&flash_lock);
|
|
return -1;
|
|
}
|
|
|
|
|
|
/**
|
|
* Erase and write data to a flash
|
|
*
|
|
* @param address Memory address to write to
|
|
* @param data Data to write
|
|
* @param len Length of the data
|
|
* @return Zero on success. Negative on failure
|
|
*/
|
|
int cvmx_flash_write(void *address, const void *data, int len)
|
|
{
|
|
int chip_id;
|
|
|
|
/* Find which chip controls this address. Don't allow the write to span
|
|
multiple chips */
|
|
for (chip_id=0; chip_id<MAX_NUM_FLASH_CHIPS; chip_id++)
|
|
{
|
|
if ((flash_info[chip_id].base_ptr <= address) &&
|
|
(flash_info[chip_id].base_ptr + flash_info[chip_id].size >= address + len))
|
|
break;
|
|
}
|
|
|
|
if (chip_id == MAX_NUM_FLASH_CHIPS)
|
|
{
|
|
cvmx_dprintf("cvmx-flash: Unable to find chip that contains address %p\n", address);
|
|
return -1;
|
|
}
|
|
|
|
cvmx_flash_t *flash = flash_info + chip_id;
|
|
|
|
/* Determine which block region we need to start writing to */
|
|
void *region_base = flash->base_ptr;
|
|
int region = 0;
|
|
while (region_base + flash->region[region].num_blocks * flash->region[region].block_size <= address)
|
|
{
|
|
region++;
|
|
region_base = flash->base_ptr + flash->region[region].start_offset;
|
|
}
|
|
|
|
/* Determine which block in the region to start at */
|
|
int block = (address - region_base) / flash->region[region].block_size;
|
|
|
|
/* Require all writes to start on block boundries */
|
|
if (address != region_base + block*flash->region[region].block_size)
|
|
{
|
|
cvmx_dprintf("cvmx-flash: Write address not aligned on a block boundry\n");
|
|
return -1;
|
|
}
|
|
|
|
/* Loop until we're out of data */
|
|
while (len > 0)
|
|
{
|
|
/* Erase the current block */
|
|
if (cvmx_flash_erase_block(chip_id, region, block))
|
|
return -1;
|
|
/* Write the new data */
|
|
if (cvmx_flash_write_block(chip_id, region, block, data))
|
|
return -1;
|
|
|
|
/* Increment to the next block */
|
|
data += flash->region[region].block_size;
|
|
len -= flash->region[region].block_size;
|
|
block++;
|
|
if (block >= flash->region[region].num_blocks)
|
|
{
|
|
block = 0;
|
|
region++;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|