04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
191 lines
5.8 KiB
ArmAsm
191 lines
5.8 KiB
ArmAsm
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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#include <machine/asm.h>
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#include <machine/regdef.h>
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.set noreorder
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.set noat
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LEAF(cvmx_interrupt_stage1)
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dla k0, cvmx_interrupt_stage2
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jalr k1, k0 // Save our address in k1, so we can tell which
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// vector we are coming from.
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nop
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END(cvmx_interrupt_stage1)
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#define STACK_SIZE (36*8)
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LEAF(cvmx_interrupt_stage2)
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dsubu sp, sp, STACK_SIZE
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sd zero, 0(sp) // Just a place holder
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sd $1, 8(sp) // start saving registers
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sd $2, 16(sp)
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sd $3, 24(sp)
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sd $4, 32(sp)
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sd $5, 40(sp)
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sd $6, 48(sp)
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sd $7, 56(sp)
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sd $8, 64(sp)
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sd $9, 72(sp)
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sd $10, 80(sp)
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sd $11, 88(sp)
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sd $12, 96(sp)
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sd $13, 104(sp)
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sd $14, 112(sp)
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sd $15, 120(sp)
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sd $16, 128(sp)
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sd $17, 136(sp)
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sd $18, 144(sp)
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sd $19, 152(sp)
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sd $20, 160(sp)
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sd $21, 168(sp)
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sd $22, 176(sp)
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sd $23, 184(sp)
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sd $24, 192(sp)
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sd $25, 200(sp)
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sd $26, 208(sp)
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sd $27, 216(sp)
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mfhi k0 // Reading lo and high takes multiple cycles
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mflo k1 // Do it here so it completes by the time we need it
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sd $28, 224(sp)
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daddu $1, sp, STACK_SIZE // Correct the SP for the space we used
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sd $1, 232(sp)
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sd $30, 240(sp)
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sd $31, 248(sp) // saved all general purpose registers
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sd k0, 256(sp) // save hi
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sd k1, 264(sp) // save lo
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/* Save DCACHE error register early, since any non-errored DCACHE accesses will clear
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** error bit */
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dmfc0 k0, $27, 1
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sd k0, 272(sp)
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/* Store DEPC for GCC's frame unwinder. */
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dmfc0 k0, $14
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sd k0, 280(sp)
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dla k0, cvmx_interrupt_in_isr
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li k1, 1
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sw k1, 0(k0)
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dla k0, cvmx_interrupt_do_irq
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jal k0
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dadd a0, sp, 0 // First argument is array of registers
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dla k0, cvmx_interrupt_in_isr
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sw $0, 0(k0)
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ld k0, 256(sp) // read hi
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ld k1, 264(sp) // read lo
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mthi k0 // restore hi
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mtlo k1 // restore lo
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ld $1, 8(sp) // start restoring registers
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ld $2, 16(sp)
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ld $3, 24(sp)
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ld $4, 32(sp)
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ld $5, 40(sp)
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ld $6, 48(sp)
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ld $7, 56(sp)
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ld $8, 64(sp)
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ld $9, 72(sp)
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ld $10, 80(sp)
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ld $11, 88(sp)
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ld $12, 96(sp)
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ld $13, 104(sp)
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ld $14, 112(sp)
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ld $15, 120(sp)
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ld $16, 128(sp)
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ld $17, 136(sp)
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ld $18, 144(sp)
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ld $19, 152(sp)
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ld $20, 160(sp)
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ld $21, 168(sp)
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ld $22, 176(sp)
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ld $23, 184(sp)
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ld $24, 192(sp)
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ld $25, 200(sp)
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ld $26, 208(sp)
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ld $28, 224(sp)
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ld $30, 240(sp)
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ld $31, 248(sp) // restored all general purpose registers
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ld $29, 232(sp) // No need to correct for STACK_SIZE
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eret
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nop
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END(cvmx_interrupt_stage2)
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// Icache and Dcache exception handler. This code is executed
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// with ERL set so we can't us virtual addresses. We save and restore
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// K0 to a global memory location so we can handle cache errors from exception
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// context. This means that if two cores get a cache exception at the same time
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// the K0 might be corrupted. This entire handler MUST fit in 128 bytes.
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#define K0_STORE_LOCATION 8
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#define DCACHE_ERROR_COUNT 16
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#define ICACHE_ERROR_COUNT 24
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LEAF(cvmx_interrupt_cache_error)
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.set push
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.set noreorder
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sd k0, K0_STORE_LOCATION($0) // Store K0 into global loc in case we're in an exception
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dmfc0 k0, $27, 1 // Get Dcache error status before any loads
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bbit0 k0, 0, not_dcache_error // Skip dcache count if no error
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dmtc0 k0, $27, 1 // Clear any Dcache errors
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ld k0, DCACHE_ERROR_COUNT($0) // Load the dcache error count
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daddu k0, 1 // Increment the dcache error count
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sd k0, DCACHE_ERROR_COUNT($0) // Store the dcache error count
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not_dcache_error:
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dmfc0 k0, $27, 0 // Get the Icache error status
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bbit0 k0, 0, not_icache_error // Skip Icache count if no error
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dmtc0 k0, $27, 0 // Clear any Icache errors
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ld k0, ICACHE_ERROR_COUNT($0) // Load the icache error count
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daddu k0, 1 // Increment the icache error count
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sd k0, ICACHE_ERROR_COUNT($0) // Store the icache error count
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not_icache_error:
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ld k0, K0_STORE_LOCATION($0) // Restore K0 since we might have been in an exception
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eret // Return from the Icache exception
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.set pop
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END(cvmx_interrupt_cache_error)
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