04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
113 lines
3.6 KiB
C
113 lines
3.6 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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#ifndef __CVMX_IXF18201_H__
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#define __CVMX_IXF18201_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Initialize the IXF18201 SPI<->XAUI MAC.
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* @return 1 on success
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* 0 on failure
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*/
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int cvmx_ixf18201_init(void);
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/**
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* Read a 16 bit register from the IXF18201
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*
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* @param reg_addr Register address
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*
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* @return 16 bit register value
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*/
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uint16_t cvmx_ixf18201_read16(uint16_t reg_addr);
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/**
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* Write a 16 bit IXF18201 register
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*
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* @param reg_addr Register address
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* @param data Value to write
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*
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*/
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void cvmx_ixf18201_write16(uint16_t reg_addr, uint16_t data);
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/**
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* Write a 16 bit IXF18201 register
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*
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* @param reg_addr Register address (must be 4 byte aligned)
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*
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* @return 32 bit register value
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*/
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uint32_t cvmx_ixf18201_read32(uint16_t reg_addr);
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/**
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* Write a 32 bit IXF18201 register
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*
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* @param reg_addr Register address (must be 4 byte aligned)
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* @param data Value to write
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*
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*/
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void cvmx_ixf18201_write32(uint16_t reg_addr, uint32_t data);
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/**
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* Performs an MII clause 45 write using the MII block in IXF18201.
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*
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* @param mii_addr Device MII address
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* @param mmd MMD address (block within device)
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* @param reg Register address
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* @param val Value to write
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*/
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void cvmx_ixf18201_mii_write(int mii_addr, int mmd, uint16_t reg, uint16_t val);
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/**
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* Performs an MII clause 45 read using the MII block in IXF18201.
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*
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* @param mii_addr Device MII address
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* @param mmd MMD address (block within device)
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* @param reg Register address
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* @return register value read from device
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*/
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int cvmx_ixf18201_mii_read(int mii_addr, int mmd, uint16_t reg);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CVMX_IXF18201_H__ */
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