04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
255 lines
9.6 KiB
C
255 lines
9.6 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-key-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon key.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_KEY_TYPEDEFS_H__
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#define __CVMX_KEY_TYPEDEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_KEY_BIST_REG CVMX_KEY_BIST_REG_FUNC()
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static inline uint64_t CVMX_KEY_BIST_REG_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
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cvmx_warn("CVMX_KEY_BIST_REG not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180020000018ull);
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}
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#else
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#define CVMX_KEY_BIST_REG (CVMX_ADD_IO_SEG(0x0001180020000018ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_KEY_CTL_STATUS CVMX_KEY_CTL_STATUS_FUNC()
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static inline uint64_t CVMX_KEY_CTL_STATUS_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
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cvmx_warn("CVMX_KEY_CTL_STATUS not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180020000010ull);
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}
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#else
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#define CVMX_KEY_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180020000010ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_KEY_INT_ENB CVMX_KEY_INT_ENB_FUNC()
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static inline uint64_t CVMX_KEY_INT_ENB_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
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cvmx_warn("CVMX_KEY_INT_ENB not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180020000008ull);
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}
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#else
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#define CVMX_KEY_INT_ENB (CVMX_ADD_IO_SEG(0x0001180020000008ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_KEY_INT_SUM CVMX_KEY_INT_SUM_FUNC()
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static inline uint64_t CVMX_KEY_INT_SUM_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
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cvmx_warn("CVMX_KEY_INT_SUM not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180020000000ull);
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}
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#else
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#define CVMX_KEY_INT_SUM (CVMX_ADD_IO_SEG(0x0001180020000000ull))
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#endif
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/**
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* cvmx_key_bist_reg
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*
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* KEY_BIST_REG = KEY's BIST Status Register
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*
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* The KEY's BIST status for memories.
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*/
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union cvmx_key_bist_reg
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{
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uint64_t u64;
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struct cvmx_key_bist_reg_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_3_63 : 61;
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uint64_t rrc : 1; /**< RRC bist status. */
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uint64_t mem1 : 1; /**< MEM - 1 bist status. */
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uint64_t mem0 : 1; /**< MEM - 0 bist status. */
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#else
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uint64_t mem0 : 1;
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uint64_t mem1 : 1;
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uint64_t rrc : 1;
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uint64_t reserved_3_63 : 61;
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#endif
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} s;
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struct cvmx_key_bist_reg_s cn38xx;
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struct cvmx_key_bist_reg_s cn38xxp2;
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struct cvmx_key_bist_reg_s cn56xx;
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struct cvmx_key_bist_reg_s cn56xxp1;
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struct cvmx_key_bist_reg_s cn58xx;
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struct cvmx_key_bist_reg_s cn58xxp1;
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struct cvmx_key_bist_reg_s cn63xx;
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struct cvmx_key_bist_reg_s cn63xxp1;
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};
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typedef union cvmx_key_bist_reg cvmx_key_bist_reg_t;
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/**
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* cvmx_key_ctl_status
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*
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* KEY_CTL_STATUS = KEY's Control/Status Register
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*
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* The KEY's interrupt enable register.
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*/
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union cvmx_key_ctl_status
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{
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uint64_t u64;
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struct cvmx_key_ctl_status_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_14_63 : 50;
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uint64_t mem1_err : 7; /**< Causes a flip of the ECC bit associated 38:32
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respective to bit 13:7 of this field, for FPF
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FIFO 1. */
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uint64_t mem0_err : 7; /**< Causes a flip of the ECC bit associated 38:32
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respective to bit 6:0 of this field, for FPF
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FIFO 0. */
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#else
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uint64_t mem0_err : 7;
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uint64_t mem1_err : 7;
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uint64_t reserved_14_63 : 50;
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#endif
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} s;
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struct cvmx_key_ctl_status_s cn38xx;
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struct cvmx_key_ctl_status_s cn38xxp2;
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struct cvmx_key_ctl_status_s cn56xx;
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struct cvmx_key_ctl_status_s cn56xxp1;
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struct cvmx_key_ctl_status_s cn58xx;
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struct cvmx_key_ctl_status_s cn58xxp1;
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struct cvmx_key_ctl_status_s cn63xx;
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struct cvmx_key_ctl_status_s cn63xxp1;
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};
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typedef union cvmx_key_ctl_status cvmx_key_ctl_status_t;
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/**
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* cvmx_key_int_enb
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*
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* KEY_INT_ENB = KEY's Interrupt Enable
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*
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* The KEY's interrupt enable register.
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*/
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union cvmx_key_int_enb
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{
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uint64_t u64;
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struct cvmx_key_int_enb_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_4_63 : 60;
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uint64_t ked1_dbe : 1; /**< When set (1) and bit 3 of the KEY_INT_SUM
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register is asserted the KEY will assert an
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interrupt. */
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uint64_t ked1_sbe : 1; /**< When set (1) and bit 2 of the KEY_INT_SUM
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register is asserted the KEY will assert an
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interrupt. */
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uint64_t ked0_dbe : 1; /**< When set (1) and bit 1 of the KEY_INT_SUM
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register is asserted the KEY will assert an
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interrupt. */
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uint64_t ked0_sbe : 1; /**< When set (1) and bit 0 of the KEY_INT_SUM
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register is asserted the KEY will assert an
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interrupt. */
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#else
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uint64_t ked0_sbe : 1;
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uint64_t ked0_dbe : 1;
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uint64_t ked1_sbe : 1;
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uint64_t ked1_dbe : 1;
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uint64_t reserved_4_63 : 60;
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#endif
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} s;
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struct cvmx_key_int_enb_s cn38xx;
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struct cvmx_key_int_enb_s cn38xxp2;
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struct cvmx_key_int_enb_s cn56xx;
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struct cvmx_key_int_enb_s cn56xxp1;
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struct cvmx_key_int_enb_s cn58xx;
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struct cvmx_key_int_enb_s cn58xxp1;
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struct cvmx_key_int_enb_s cn63xx;
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struct cvmx_key_int_enb_s cn63xxp1;
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};
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typedef union cvmx_key_int_enb cvmx_key_int_enb_t;
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/**
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* cvmx_key_int_sum
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*
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* KEY_INT_SUM = KEY's Interrupt Summary Register
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*
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* Contains the diffrent interrupt summary bits of the KEY.
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*/
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union cvmx_key_int_sum
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{
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uint64_t u64;
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struct cvmx_key_int_sum_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_4_63 : 60;
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uint64_t ked1_dbe : 1;
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uint64_t ked1_sbe : 1;
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uint64_t ked0_dbe : 1;
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uint64_t ked0_sbe : 1;
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#else
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uint64_t ked0_sbe : 1;
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uint64_t ked0_dbe : 1;
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uint64_t ked1_sbe : 1;
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uint64_t ked1_dbe : 1;
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uint64_t reserved_4_63 : 60;
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#endif
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} s;
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struct cvmx_key_int_sum_s cn38xx;
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struct cvmx_key_int_sum_s cn38xxp2;
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struct cvmx_key_int_sum_s cn56xx;
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struct cvmx_key_int_sum_s cn56xxp1;
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struct cvmx_key_int_sum_s cn58xx;
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struct cvmx_key_int_sum_s cn58xxp1;
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struct cvmx_key_int_sum_s cn63xx;
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struct cvmx_key_int_sum_s cn63xxp1;
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};
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typedef union cvmx_key_int_sum cvmx_key_int_sum_t;
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#endif
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