04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
657 lines
23 KiB
C
657 lines
23 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-led-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon led.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_LED_TYPEDEFS_H__
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#define __CVMX_LED_TYPEDEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_LED_BLINK CVMX_LED_BLINK_FUNC()
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static inline uint64_t CVMX_LED_BLINK_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
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cvmx_warn("CVMX_LED_BLINK not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180000001A48ull);
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}
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#else
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#define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_LED_CLK_PHASE CVMX_LED_CLK_PHASE_FUNC()
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static inline uint64_t CVMX_LED_CLK_PHASE_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
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cvmx_warn("CVMX_LED_CLK_PHASE not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180000001A08ull);
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}
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#else
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#define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_LED_CYLON CVMX_LED_CYLON_FUNC()
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static inline uint64_t CVMX_LED_CYLON_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
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cvmx_warn("CVMX_LED_CYLON not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180000001AF8ull);
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}
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#else
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#define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_LED_DBG CVMX_LED_DBG_FUNC()
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static inline uint64_t CVMX_LED_DBG_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
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cvmx_warn("CVMX_LED_DBG not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180000001A18ull);
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}
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#else
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#define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_LED_EN CVMX_LED_EN_FUNC()
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static inline uint64_t CVMX_LED_EN_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
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cvmx_warn("CVMX_LED_EN not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180000001A00ull);
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}
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#else
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#define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_LED_POLARITY CVMX_LED_POLARITY_FUNC()
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static inline uint64_t CVMX_LED_POLARITY_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
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cvmx_warn("CVMX_LED_POLARITY not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180000001A50ull);
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}
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#else
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#define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_LED_PRT CVMX_LED_PRT_FUNC()
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static inline uint64_t CVMX_LED_PRT_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
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cvmx_warn("CVMX_LED_PRT not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180000001A10ull);
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}
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#else
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#define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_LED_PRT_FMT CVMX_LED_PRT_FMT_FUNC()
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static inline uint64_t CVMX_LED_PRT_FMT_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
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cvmx_warn("CVMX_LED_PRT_FMT not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180000001A30ull);
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}
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#else
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#define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_LED_PRT_STATUSX(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
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(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
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(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7)))))
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cvmx_warn("CVMX_LED_PRT_STATUSX(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8;
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}
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#else
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#define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_LED_UDD_CNTX(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
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cvmx_warn("CVMX_LED_UDD_CNTX(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8;
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}
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#else
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#define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_LED_UDD_DATX(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
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cvmx_warn("CVMX_LED_UDD_DATX(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8;
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}
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#else
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#define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_LED_UDD_DAT_CLRX(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
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cvmx_warn("CVMX_LED_UDD_DAT_CLRX(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16;
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}
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#else
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#define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_LED_UDD_DAT_SETX(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
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cvmx_warn("CVMX_LED_UDD_DAT_SETX(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16;
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}
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#else
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#define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
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#endif
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/**
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* cvmx_led_blink
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*
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* LED_BLINK = LED Blink Rate (in led_clks)
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*
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*/
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union cvmx_led_blink
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{
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uint64_t u64;
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struct cvmx_led_blink_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_8_63 : 56;
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uint64_t rate : 8; /**< LED Blink rate in led_latch clks
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RATE must be > 0 */
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#else
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uint64_t rate : 8;
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uint64_t reserved_8_63 : 56;
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#endif
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} s;
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struct cvmx_led_blink_s cn38xx;
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struct cvmx_led_blink_s cn38xxp2;
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struct cvmx_led_blink_s cn56xx;
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struct cvmx_led_blink_s cn56xxp1;
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struct cvmx_led_blink_s cn58xx;
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struct cvmx_led_blink_s cn58xxp1;
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};
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typedef union cvmx_led_blink cvmx_led_blink_t;
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/**
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* cvmx_led_clk_phase
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*
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* LED_CLK_PHASE = LED Clock Phase (in 64 eclks)
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*
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*
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* Notes:
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* Example:
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* Given a 2ns eclk, an LED_CLK_PHASE[PHASE] = 1, indicates that each
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* led_clk phase is 64 eclks, or 128ns. The led_clk period is 2*phase,
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* or 256ns which is 3.9MHz. The default value of 4, yields an led_clk
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* period of 64*4*2ns*2 = 1024ns or ~1MHz (977KHz).
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*/
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union cvmx_led_clk_phase
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{
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uint64_t u64;
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struct cvmx_led_clk_phase_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_7_63 : 57;
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uint64_t phase : 7; /**< Number of 64 eclks in order to create the led_clk */
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#else
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uint64_t phase : 7;
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uint64_t reserved_7_63 : 57;
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#endif
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} s;
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struct cvmx_led_clk_phase_s cn38xx;
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struct cvmx_led_clk_phase_s cn38xxp2;
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struct cvmx_led_clk_phase_s cn56xx;
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struct cvmx_led_clk_phase_s cn56xxp1;
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struct cvmx_led_clk_phase_s cn58xx;
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struct cvmx_led_clk_phase_s cn58xxp1;
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};
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typedef union cvmx_led_clk_phase cvmx_led_clk_phase_t;
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/**
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* cvmx_led_cylon
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*
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* LED_CYLON = LED CYLON Effect (should remain undocumented)
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*
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*/
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union cvmx_led_cylon
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{
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uint64_t u64;
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struct cvmx_led_cylon_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_16_63 : 48;
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uint64_t rate : 16; /**< LED Cylon Effect when RATE!=0
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Changes at RATE*LATCH period */
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#else
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uint64_t rate : 16;
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uint64_t reserved_16_63 : 48;
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#endif
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} s;
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struct cvmx_led_cylon_s cn38xx;
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struct cvmx_led_cylon_s cn38xxp2;
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struct cvmx_led_cylon_s cn56xx;
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struct cvmx_led_cylon_s cn56xxp1;
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struct cvmx_led_cylon_s cn58xx;
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struct cvmx_led_cylon_s cn58xxp1;
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};
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typedef union cvmx_led_cylon cvmx_led_cylon_t;
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/**
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* cvmx_led_dbg
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*
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* LED_DBG = LED Debug Port information
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*
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*/
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union cvmx_led_dbg
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{
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uint64_t u64;
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struct cvmx_led_dbg_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_1_63 : 63;
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uint64_t dbg_en : 1; /**< Add Debug Port Data to the LED shift chain
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Debug Data is shifted out LSB to MSB */
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#else
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uint64_t dbg_en : 1;
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uint64_t reserved_1_63 : 63;
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#endif
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} s;
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struct cvmx_led_dbg_s cn38xx;
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struct cvmx_led_dbg_s cn38xxp2;
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struct cvmx_led_dbg_s cn56xx;
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struct cvmx_led_dbg_s cn56xxp1;
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struct cvmx_led_dbg_s cn58xx;
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struct cvmx_led_dbg_s cn58xxp1;
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};
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typedef union cvmx_led_dbg cvmx_led_dbg_t;
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/**
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* cvmx_led_en
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*
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* LED_EN = LED Interface Enable
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*
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*
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* Notes:
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* The LED interface is comprised of a shift chain with a parallel latch. LED
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* data is shifted out on each fallingg edge of led_clk and then captured by
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* led_lat.
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*
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* The LED shift chain is comprised of the following...
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*
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* 32 - UDD header
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* 6x8 - per port status
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* 17 - debug port
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* 32 - UDD trailer
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*
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* for a total of 129 bits.
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*
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* UDD header is programmable from 0-32 bits (LED_UDD_CNT0) and will shift out
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* LSB to MSB (LED_UDD_DAT0[0], LED_UDD_DAT0[1],
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* ... LED_UDD_DAT0[LED_UDD_CNT0].
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*
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* The per port status is also variable. Systems can control which ports send
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* data (LED_PRT) as well as the status content (LED_PRT_FMT and
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* LED_PRT_STATUS*). When multiple ports are enabled, they come out in lowest
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* port to highest port (prt0, prt1, ...).
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*
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* The debug port data can also be added to the LED chain (LED_DBG). When
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* enabled, the debug data shifts out LSB to MSB.
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*
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* The UDD trailer data is identical to the header data, but uses LED_UDD_CNT1
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* and LED_UDD_DAT1.
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*/
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union cvmx_led_en
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{
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uint64_t u64;
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struct cvmx_led_en_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_1_63 : 63;
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uint64_t en : 1; /**< Enable the LED interface shift-chain */
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#else
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uint64_t en : 1;
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uint64_t reserved_1_63 : 63;
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#endif
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} s;
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struct cvmx_led_en_s cn38xx;
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struct cvmx_led_en_s cn38xxp2;
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struct cvmx_led_en_s cn56xx;
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struct cvmx_led_en_s cn56xxp1;
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struct cvmx_led_en_s cn58xx;
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struct cvmx_led_en_s cn58xxp1;
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};
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typedef union cvmx_led_en cvmx_led_en_t;
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/**
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* cvmx_led_polarity
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*
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* LED_POLARITY = LED Polarity
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*
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*/
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union cvmx_led_polarity
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{
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uint64_t u64;
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struct cvmx_led_polarity_s
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{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_1_63 : 63;
|
|
uint64_t polarity : 1; /**< LED active polarity
|
|
0 = active HIGH LED
|
|
1 = active LOW LED (invert led_dat) */
|
|
#else
|
|
uint64_t polarity : 1;
|
|
uint64_t reserved_1_63 : 63;
|
|
#endif
|
|
} s;
|
|
struct cvmx_led_polarity_s cn38xx;
|
|
struct cvmx_led_polarity_s cn38xxp2;
|
|
struct cvmx_led_polarity_s cn56xx;
|
|
struct cvmx_led_polarity_s cn56xxp1;
|
|
struct cvmx_led_polarity_s cn58xx;
|
|
struct cvmx_led_polarity_s cn58xxp1;
|
|
};
|
|
typedef union cvmx_led_polarity cvmx_led_polarity_t;
|
|
|
|
/**
|
|
* cvmx_led_prt
|
|
*
|
|
* LED_PRT = LED Port status information
|
|
*
|
|
*
|
|
* Notes:
|
|
* Note:
|
|
* the PRT vector enables information of the 8 RGMII ports connected to
|
|
* Octane. It does not reflect the actual programmed PHY addresses.
|
|
*/
|
|
union cvmx_led_prt
|
|
{
|
|
uint64_t u64;
|
|
struct cvmx_led_prt_s
|
|
{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_8_63 : 56;
|
|
uint64_t prt_en : 8; /**< Which ports are enabled to display status
|
|
PRT_EN<3:0> coresponds to RGMII ports 3-0 on int0
|
|
PRT_EN<7:4> coresponds to RGMII ports 7-4 on int1
|
|
Only applies when interface is in RGMII mode
|
|
The status format is defined by LED_PRT_FMT */
|
|
#else
|
|
uint64_t prt_en : 8;
|
|
uint64_t reserved_8_63 : 56;
|
|
#endif
|
|
} s;
|
|
struct cvmx_led_prt_s cn38xx;
|
|
struct cvmx_led_prt_s cn38xxp2;
|
|
struct cvmx_led_prt_s cn56xx;
|
|
struct cvmx_led_prt_s cn56xxp1;
|
|
struct cvmx_led_prt_s cn58xx;
|
|
struct cvmx_led_prt_s cn58xxp1;
|
|
};
|
|
typedef union cvmx_led_prt cvmx_led_prt_t;
|
|
|
|
/**
|
|
* cvmx_led_prt_fmt
|
|
*
|
|
* LED_PRT_FMT = LED Port Status Infomation Format
|
|
*
|
|
*
|
|
* Notes:
|
|
* TX: RGMII TX block is sending packet data or extends on the port
|
|
* RX: RGMII RX block has received non-idle cycle
|
|
*
|
|
* For short transfers, LEDs will remain on for at least one blink cycle
|
|
*/
|
|
union cvmx_led_prt_fmt
|
|
{
|
|
uint64_t u64;
|
|
struct cvmx_led_prt_fmt_s
|
|
{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_4_63 : 60;
|
|
uint64_t format : 4; /**< Port Status Information for each enabled port in
|
|
LED_PRT. The formats are below
|
|
0x0: [ LED_PRT_STATUS[0] ]
|
|
0x1: [ LED_PRT_STATUS[1:0] ]
|
|
0x2: [ LED_PRT_STATUS[3:0] ]
|
|
0x3: [ LED_PRT_STATUS[5:0] ]
|
|
0x4: [ (RX|TX), LED_PRT_STATUS[0] ]
|
|
0x5: [ (RX|TX), LED_PRT_STATUS[1:0] ]
|
|
0x6: [ (RX|TX), LED_PRT_STATUS[3:0] ]
|
|
0x8: [ Tx, Rx, LED_PRT_STATUS[0] ]
|
|
0x9: [ Tx, Rx, LED_PRT_STATUS[1:0] ]
|
|
0xa: [ Tx, Rx, LED_PRT_STATUS[3:0] ] */
|
|
#else
|
|
uint64_t format : 4;
|
|
uint64_t reserved_4_63 : 60;
|
|
#endif
|
|
} s;
|
|
struct cvmx_led_prt_fmt_s cn38xx;
|
|
struct cvmx_led_prt_fmt_s cn38xxp2;
|
|
struct cvmx_led_prt_fmt_s cn56xx;
|
|
struct cvmx_led_prt_fmt_s cn56xxp1;
|
|
struct cvmx_led_prt_fmt_s cn58xx;
|
|
struct cvmx_led_prt_fmt_s cn58xxp1;
|
|
};
|
|
typedef union cvmx_led_prt_fmt cvmx_led_prt_fmt_t;
|
|
|
|
/**
|
|
* cvmx_led_prt_status#
|
|
*
|
|
* LED_PRT_STATUS = LED Port Status information
|
|
*
|
|
*/
|
|
union cvmx_led_prt_statusx
|
|
{
|
|
uint64_t u64;
|
|
struct cvmx_led_prt_statusx_s
|
|
{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_6_63 : 58;
|
|
uint64_t status : 6; /**< Bits that software can set to be added to the
|
|
LED shift chain - depending on LED_PRT_FMT
|
|
LED_PRT_STATUS(3..0) corespond to RGMII ports 3-0
|
|
on interface0
|
|
LED_PRT_STATUS(7..4) corespond to RGMII ports 7-4
|
|
on interface1
|
|
Only applies when interface is in RGMII mode */
|
|
#else
|
|
uint64_t status : 6;
|
|
uint64_t reserved_6_63 : 58;
|
|
#endif
|
|
} s;
|
|
struct cvmx_led_prt_statusx_s cn38xx;
|
|
struct cvmx_led_prt_statusx_s cn38xxp2;
|
|
struct cvmx_led_prt_statusx_s cn56xx;
|
|
struct cvmx_led_prt_statusx_s cn56xxp1;
|
|
struct cvmx_led_prt_statusx_s cn58xx;
|
|
struct cvmx_led_prt_statusx_s cn58xxp1;
|
|
};
|
|
typedef union cvmx_led_prt_statusx cvmx_led_prt_statusx_t;
|
|
|
|
/**
|
|
* cvmx_led_udd_cnt#
|
|
*
|
|
* LED_UDD_CNT = LED UDD Counts
|
|
*
|
|
*/
|
|
union cvmx_led_udd_cntx
|
|
{
|
|
uint64_t u64;
|
|
struct cvmx_led_udd_cntx_s
|
|
{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_6_63 : 58;
|
|
uint64_t cnt : 6; /**< Number of bits of user-defined data to include in
|
|
the LED shift chain. Legal values: 0-32. */
|
|
#else
|
|
uint64_t cnt : 6;
|
|
uint64_t reserved_6_63 : 58;
|
|
#endif
|
|
} s;
|
|
struct cvmx_led_udd_cntx_s cn38xx;
|
|
struct cvmx_led_udd_cntx_s cn38xxp2;
|
|
struct cvmx_led_udd_cntx_s cn56xx;
|
|
struct cvmx_led_udd_cntx_s cn56xxp1;
|
|
struct cvmx_led_udd_cntx_s cn58xx;
|
|
struct cvmx_led_udd_cntx_s cn58xxp1;
|
|
};
|
|
typedef union cvmx_led_udd_cntx cvmx_led_udd_cntx_t;
|
|
|
|
/**
|
|
* cvmx_led_udd_dat#
|
|
*
|
|
* LED_UDD_DAT = User defined data (header or trailer)
|
|
*
|
|
*
|
|
* Notes:
|
|
* Bits come out LSB to MSB on the shift chain. If LED_UDD_CNT is set to 4
|
|
* then the bits comes out LED_UDD_DAT[0], LED_UDD_DAT[1], LED_UDD_DAT[2],
|
|
* LED_UDD_DAT[3].
|
|
*/
|
|
union cvmx_led_udd_datx
|
|
{
|
|
uint64_t u64;
|
|
struct cvmx_led_udd_datx_s
|
|
{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_32_63 : 32;
|
|
uint64_t dat : 32; /**< Header or trailer UDD data to be displayed on
|
|
the LED shift chain. Number of bits to include
|
|
is controled by LED_UDD_CNT */
|
|
#else
|
|
uint64_t dat : 32;
|
|
uint64_t reserved_32_63 : 32;
|
|
#endif
|
|
} s;
|
|
struct cvmx_led_udd_datx_s cn38xx;
|
|
struct cvmx_led_udd_datx_s cn38xxp2;
|
|
struct cvmx_led_udd_datx_s cn56xx;
|
|
struct cvmx_led_udd_datx_s cn56xxp1;
|
|
struct cvmx_led_udd_datx_s cn58xx;
|
|
struct cvmx_led_udd_datx_s cn58xxp1;
|
|
};
|
|
typedef union cvmx_led_udd_datx cvmx_led_udd_datx_t;
|
|
|
|
/**
|
|
* cvmx_led_udd_dat_clr#
|
|
*
|
|
* LED_UDD_DAT_CLR = User defined data (header or trailer)
|
|
*
|
|
*/
|
|
union cvmx_led_udd_dat_clrx
|
|
{
|
|
uint64_t u64;
|
|
struct cvmx_led_udd_dat_clrx_s
|
|
{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_32_63 : 32;
|
|
uint64_t clr : 32; /**< Bitwise clear for the Header or trailer UDD data to
|
|
be displayed on the LED shift chain. */
|
|
#else
|
|
uint64_t clr : 32;
|
|
uint64_t reserved_32_63 : 32;
|
|
#endif
|
|
} s;
|
|
struct cvmx_led_udd_dat_clrx_s cn38xx;
|
|
struct cvmx_led_udd_dat_clrx_s cn38xxp2;
|
|
struct cvmx_led_udd_dat_clrx_s cn56xx;
|
|
struct cvmx_led_udd_dat_clrx_s cn56xxp1;
|
|
struct cvmx_led_udd_dat_clrx_s cn58xx;
|
|
struct cvmx_led_udd_dat_clrx_s cn58xxp1;
|
|
};
|
|
typedef union cvmx_led_udd_dat_clrx cvmx_led_udd_dat_clrx_t;
|
|
|
|
/**
|
|
* cvmx_led_udd_dat_set#
|
|
*
|
|
* LED_UDD_DAT_SET = User defined data (header or trailer)
|
|
*
|
|
*/
|
|
union cvmx_led_udd_dat_setx
|
|
{
|
|
uint64_t u64;
|
|
struct cvmx_led_udd_dat_setx_s
|
|
{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_32_63 : 32;
|
|
uint64_t set : 32; /**< Bitwise set for the Header or trailer UDD data to
|
|
be displayed on the LED shift chain. */
|
|
#else
|
|
uint64_t set : 32;
|
|
uint64_t reserved_32_63 : 32;
|
|
#endif
|
|
} s;
|
|
struct cvmx_led_udd_dat_setx_s cn38xx;
|
|
struct cvmx_led_udd_dat_setx_s cn38xxp2;
|
|
struct cvmx_led_udd_dat_setx_s cn56xx;
|
|
struct cvmx_led_udd_dat_setx_s cn56xxp1;
|
|
struct cvmx_led_udd_dat_setx_s cn58xx;
|
|
struct cvmx_led_udd_dat_setx_s cn58xxp1;
|
|
};
|
|
typedef union cvmx_led_udd_dat_setx cvmx_led_udd_dat_setx_t;
|
|
|
|
#endif
|