04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
322 lines
10 KiB
C
322 lines
10 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Interface to PCIe as a host(RC) or target(EP)
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*
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* <hr>$Revision: 52004 $<hr>
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*/
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#ifndef __CVMX_PCIE_H__
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#define __CVMX_PCIE_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* The physical memory base mapped by BAR1. 256MB at the end of the
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* first 4GB.
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*/
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#define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28))
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#define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28)
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/*
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* The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
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* place BAR1 so it is the same for both.
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*/
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#define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
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typedef union
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{
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uint64_t u64;
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struct
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{
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uint64_t upper : 2; /* Normally 2 for XKPHYS */
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uint64_t reserved_49_61 : 13; /* Must be zero */
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uint64_t io : 1; /* 1 for IO space access */
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uint64_t did : 5; /* PCIe DID = 3 */
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uint64_t subdid : 3; /* PCIe SubDID = 1 */
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uint64_t reserved_36_39 : 4; /* Must be zero */
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uint64_t es : 2; /* Endian swap = 1 */
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uint64_t port : 2; /* PCIe port 0,1 */
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uint64_t reserved_29_31 : 3; /* Must be zero */
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uint64_t ty : 1; /* Selects the type of the configuration request (0 = type 0, 1 = type 1). */
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uint64_t bus : 8; /* Target bus number sent in the ID in the request. */
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uint64_t dev : 5; /* Target device number sent in the ID in the request. Note that Dev must be
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zero for type 0 configuration requests. */
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uint64_t func : 3; /* Target function number sent in the ID in the request. */
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uint64_t reg : 12; /* Selects a register in the configuration space of the target. */
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} config;
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struct
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{
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uint64_t upper : 2; /* Normally 2 for XKPHYS */
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uint64_t reserved_49_61 : 13; /* Must be zero */
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uint64_t io : 1; /* 1 for IO space access */
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uint64_t did : 5; /* PCIe DID = 3 */
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uint64_t subdid : 3; /* PCIe SubDID = 2 */
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uint64_t reserved_36_39 : 4; /* Must be zero */
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uint64_t es : 2; /* Endian swap = 1 */
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uint64_t port : 2; /* PCIe port 0,1 */
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uint64_t address : 32; /* PCIe IO address */
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} io;
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struct
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{
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uint64_t upper : 2; /* Normally 2 for XKPHYS */
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uint64_t reserved_49_61 : 13; /* Must be zero */
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uint64_t io : 1; /* 1 for IO space access */
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uint64_t did : 5; /* PCIe DID = 3 */
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uint64_t subdid : 3; /* PCIe SubDID = 3-6 */
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uint64_t reserved_36_39 : 4; /* Must be zero */
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uint64_t address : 36; /* PCIe Mem address */
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} mem;
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} cvmx_pcie_address_t;
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/**
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* Return the Core virtual base address for PCIe IO access. IOs are
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* read/written as an offset from this address.
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*
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* @param pcie_port PCIe port the IO is for
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*
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* @return 64bit Octeon IO base address for read/write
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*/
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uint64_t cvmx_pcie_get_io_base_address(int pcie_port);
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/**
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* Size of the IO address region returned at address
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* cvmx_pcie_get_io_base_address()
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*
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* @param pcie_port PCIe port the IO is for
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*
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* @return Size of the IO window
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*/
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uint64_t cvmx_pcie_get_io_size(int pcie_port);
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/**
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* Return the Core virtual base address for PCIe MEM access. Memory is
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* read/written as an offset from this address.
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*
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* @param pcie_port PCIe port the IO is for
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*
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* @return 64bit Octeon IO base address for read/write
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*/
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uint64_t cvmx_pcie_get_mem_base_address(int pcie_port);
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/**
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* Size of the Mem address region returned at address
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* cvmx_pcie_get_mem_base_address()
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*
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* @param pcie_port PCIe port the IO is for
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*
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* @return Size of the Mem window
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*/
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uint64_t cvmx_pcie_get_mem_size(int pcie_port);
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/**
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* Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
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*
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* @param pcie_port PCIe port to initialize
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*
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* @return Zero on success
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*/
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int cvmx_pcie_rc_initialize(int pcie_port);
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/**
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* Shutdown a PCIe port and put it in reset
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*
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* @param pcie_port PCIe port to shutdown
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*
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* @return Zero on success
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*/
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int cvmx_pcie_rc_shutdown(int pcie_port);
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/**
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* Read 8bits from a Device's config space
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*
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* @param pcie_port PCIe port the device is on
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* @param bus Sub bus
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* @param dev Device ID
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* @param fn Device sub function
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* @param reg Register to access
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*
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* @return Result of the read
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*/
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uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev, int fn, int reg);
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/**
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* Read 16bits from a Device's config space
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*
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* @param pcie_port PCIe port the device is on
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* @param bus Sub bus
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* @param dev Device ID
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* @param fn Device sub function
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* @param reg Register to access
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*
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* @return Result of the read
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*/
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uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn, int reg);
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/**
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* Read 32bits from a Device's config space
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*
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* @param pcie_port PCIe port the device is on
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* @param bus Sub bus
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* @param dev Device ID
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* @param fn Device sub function
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* @param reg Register to access
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*
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* @return Result of the read
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*/
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uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn, int reg);
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/**
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* Write 8bits to a Device's config space
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*
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* @param pcie_port PCIe port the device is on
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* @param bus Sub bus
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* @param dev Device ID
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* @param fn Device sub function
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* @param reg Register to access
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* @param val Value to write
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*/
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void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, int reg, uint8_t val);
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/**
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* Write 16bits to a Device's config space
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*
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* @param pcie_port PCIe port the device is on
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* @param bus Sub bus
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* @param dev Device ID
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* @param fn Device sub function
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* @param reg Register to access
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* @param val Value to write
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*/
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void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, int reg, uint16_t val);
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/**
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* Write 32bits to a Device's config space
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*
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* @param pcie_port PCIe port the device is on
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* @param bus Sub bus
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* @param dev Device ID
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* @param fn Device sub function
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* @param reg Register to access
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* @param val Value to write
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*/
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void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg, uint32_t val);
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/**
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* Read a PCIe config space register indirectly. This is used for
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* registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
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*
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* @param pcie_port PCIe port to read from
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* @param cfg_offset Address to read
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*
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* @return Value read
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*/
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uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset);
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/**
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* Write a PCIe config space register indirectly. This is used for
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* registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
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*
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* @param pcie_port PCIe port to write to
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* @param cfg_offset Address to write
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* @param val Value to write
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*/
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void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val);
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/**
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* Write a 32bit value to the Octeon NPEI register space
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*
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* @param address Address to write to
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* @param val Value to write
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*/
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static inline void cvmx_pcie_npei_write32(uint64_t address, uint32_t val)
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{
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cvmx_write64_uint32(address ^ 4, val);
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cvmx_read64_uint32(address ^ 4);
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}
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/**
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* Read a 32bit value from the Octeon NPEI register space
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*
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* @param address Address to read
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* @return The result
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*/
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static inline uint32_t cvmx_pcie_npei_read32(uint64_t address)
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{
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return cvmx_read64_uint32(address ^ 4);
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}
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/**
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* Initialize a PCIe port for use in target(EP) mode.
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*
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* @param pcie_port PCIe port to initialize
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*
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* @return Zero on success
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*/
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int cvmx_pcie_ep_initialize(int pcie_port);
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/**
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* Wait for posted PCIe read/writes to reach the other side of
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* the internal PCIe switch. This will insure that core
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* read/writes are posted before anything after this function
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* is called. This may be necessary when writing to memory that
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* will later be read using the DMA/PKT engines.
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*
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* @param pcie_port PCIe port to wait for
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*/
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void cvmx_pcie_wait_for_pending(int pcie_port);
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#ifdef __cplusplus
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}
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#endif
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#endif
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