eb8a7632ba
original, this hides the contents of cam_compat.h from ktrace/kdump/truss, avoiding problems there. There are no user-servicable parts in there, so no need for those tools to be groping around in there. Approved by: re
491 lines
14 KiB
C
491 lines
14 KiB
C
/*
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* HighPoint RR3xxx/4xxx RAID Driver for FreeBSD
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* Copyright (C) 2007-2012 HighPoint Technologies, Inc. All Rights Reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _HPTIOP_H
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#define _HPTIOP_H
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define DBG 0
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#ifdef DBG
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int hpt_iop_dbg_level = 0;
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#define KdPrint(x) do { if (hpt_iop_dbg_level) printf x; } while (0)
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#define HPT_ASSERT(x) assert(x)
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#else
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#define KdPrint(x)
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#define HPT_ASSERT(x)
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#endif
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#define HPT_SRB_MAX_REQ_SIZE 600
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#define HPT_SRB_MAX_QUEUE_SIZE 0x100
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/* beyond 64G mem */
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#define HPT_SRB_FLAG_HIGH_MEM_ACESS 0x1
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#define HPT_SRB_MAX_SIZE ((sizeof(struct hpt_iop_srb) + 0x1f) & ~0x1f)
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#ifndef offsetof
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#define offsetof(TYPE, MEM) ((size_t)&((TYPE*)0)->MEM)
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#endif
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#ifndef MIN
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#define MIN(a, b) ((a) < (b) ? (a) : (b))
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#endif
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#define HPT_IOCTL_MAGIC 0xA1B2C3D4
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#define HPT_IOCTL_MAGIC32 0x1A2B3C4D
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struct hpt_iopmu_itl {
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u_int32_t resrved0[4];
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u_int32_t inbound_msgaddr0;
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u_int32_t inbound_msgaddr1;
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u_int32_t outbound_msgaddr0;
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u_int32_t outbound_msgaddr1;
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u_int32_t inbound_doorbell;
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u_int32_t inbound_intstatus;
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u_int32_t inbound_intmask;
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u_int32_t outbound_doorbell;
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u_int32_t outbound_intstatus;
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u_int32_t outbound_intmask;
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u_int32_t reserved1[2];
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u_int32_t inbound_queue;
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u_int32_t outbound_queue;
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};
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#define IOPMU_QUEUE_EMPTY 0xffffffff
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#define IOPMU_QUEUE_MASK_HOST_BITS 0xf0000000
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#define IOPMU_QUEUE_ADDR_HOST_BIT 0x80000000
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#define IOPMU_QUEUE_REQUEST_SIZE_BIT 0x40000000
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#define IOPMU_QUEUE_REQUEST_RESULT_BIT 0x40000000
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#define IOPMU_MAX_MEM_SUPPORT_MASK_64G 0xfffffff000000000ull
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#define IOPMU_MAX_MEM_SUPPORT_MASK_32G 0xfffffff800000000ull
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#define IOPMU_OUTBOUND_INT_MSG0 1
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#define IOPMU_OUTBOUND_INT_MSG1 2
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#define IOPMU_OUTBOUND_INT_DOORBELL 4
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#define IOPMU_OUTBOUND_INT_POSTQUEUE 8
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#define IOPMU_OUTBOUND_INT_PCI 0x10
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#define IOPMU_INBOUND_INT_MSG0 1
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#define IOPMU_INBOUND_INT_MSG1 2
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#define IOPMU_INBOUND_INT_DOORBELL 4
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#define IOPMU_INBOUND_INT_ERROR 8
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#define IOPMU_INBOUND_INT_POSTQUEUE 0x10
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#define MVIOP_QUEUE_LEN 512
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struct hpt_iopmu_mv {
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u_int32_t inbound_head;
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u_int32_t inbound_tail;
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u_int32_t outbound_head;
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u_int32_t outbound_tail;
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u_int32_t inbound_msg;
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u_int32_t outbound_msg;
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u_int32_t reserve[10];
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u_int64_t inbound_q[MVIOP_QUEUE_LEN];
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u_int64_t outbound_q[MVIOP_QUEUE_LEN];
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};
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struct hpt_iopmv_regs {
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u_int32_t reserved[0x20400 / 4];
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u_int32_t inbound_doorbell;
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u_int32_t inbound_intmask;
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u_int32_t outbound_doorbell;
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u_int32_t outbound_intmask;
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};
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#define CL_POINTER_TOGGLE 0x00004000
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#define CPU_TO_F0_DRBL_MSG_A_BIT 0x02000000
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#pragma pack(1)
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struct hpt_iopmu_mvfrey {
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u_int32_t reserved[0x4000 / 4];
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/* hpt_frey_com_reg */
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u_int32_t inbound_base; /* 0x4000 : 0 */
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u_int32_t inbound_base_high; /* 4 */
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u_int32_t reserved2[(0x18 - 8)/ 4];
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u_int32_t inbound_write_ptr; /* 0x18 */
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u_int32_t inbound_read_ptr; /* 0x1c */
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u_int32_t reserved3[(0x2c - 0x20) / 4];
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u_int32_t inbound_conf_ctl; /* 0x2c */
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u_int32_t reserved4[(0x50 - 0x30) / 4];
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u_int32_t outbound_base; /* 0x50 */
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u_int32_t outbound_base_high; /* 0x54 */
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u_int32_t outbound_shadow_base; /* 0x58 */
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u_int32_t outbound_shadow_base_high; /* 0x5c */
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u_int32_t reserved5[(0x68 - 0x60) / 4];
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u_int32_t outbound_write; /* 0x68 */
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u_int32_t reserved6[(0x70 - 0x6c) / 4];
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u_int32_t outbound_read; /* 0x70 */
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u_int32_t reserved7[(0x88 - 0x74) / 4];
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u_int32_t isr_cause; /* 0x88 */
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u_int32_t isr_enable; /* 0x8c */
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u_int32_t reserved8[(0x10200 - 0x4090) / 4];
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/* hpt_frey_intr_ctl intr_ctl */
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u_int32_t main_int_cuase; /* 0x10200: 0 */
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u_int32_t main_irq_enable; /* 4 */
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u_int32_t main_fiq_enable; /* 8 */
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u_int32_t pcie_f0_int_enable; /* 0xc */
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u_int32_t pcie_f1_int_enable; /* 0x10 */
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u_int32_t pcie_f2_int_enable; /* 0x14 */
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u_int32_t pcie_f3_int_enable; /* 0x18 */
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u_int32_t reserved9[(0x10400 - 0x1021c) / 4];
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/* hpt_frey_msg_drbl */
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u_int32_t f0_to_cpu_msg_a; /* 0x10400: 0 */
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u_int32_t reserved10[(0x20 - 4) / 4];
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u_int32_t cpu_to_f0_msg_a; /* 0x20 */
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u_int32_t reserved11[(0x80 - 0x24) / 4];
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u_int32_t f0_doorbell; /* 0x80 */
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u_int32_t f0_doorbell_enable; /* 0x84 */
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};
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struct mvfrey_inlist_entry {
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u_int64_t addr;
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u_int32_t intrfc_len;
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u_int32_t reserved;
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};
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struct mvfrey_outlist_entry {
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u_int32_t val;
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};
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#pragma pack()
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#define MVIOP_IOCTLCFG_SIZE 0x800
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#define MVIOP_MU_QUEUE_ADDR_HOST_MASK (~(0x1full))
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#define MVIOP_MU_QUEUE_ADDR_HOST_BIT 4
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#define MVIOP_MU_QUEUE_ADDR_IOP_HIGH32 0xffffffff
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#define MVIOP_MU_QUEUE_REQUEST_RESULT_BIT 1
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#define MVIOP_MU_QUEUE_REQUEST_RETURN_CONTEXT 2
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#define MVIOP_MU_INBOUND_INT_MSG 1
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#define MVIOP_MU_INBOUND_INT_POSTQUEUE 2
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#define MVIOP_MU_OUTBOUND_INT_MSG 1
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#define MVIOP_MU_OUTBOUND_INT_POSTQUEUE 2
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#define MVIOP_CMD_TYPE_GET_CONFIG (1 << 5)
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#define MVIOP_CMD_TYPE_SET_CONFIG (1 << 6)
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#define MVIOP_CMD_TYPE_SCSI (1 << 7)
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#define MVIOP_CMD_TYPE_IOCTL (1 << 8)
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#define MVIOP_CMD_TYPE_BLOCK (1 << 9)
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#define MVIOP_REQUEST_NUMBER_START_BIT 16
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#define MVFREYIOPMU_QUEUE_REQUEST_RESULT_BIT 0x40000000
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enum hpt_iopmu_message {
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/* host-to-iop messages */
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IOPMU_INBOUND_MSG0_NOP = 0,
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IOPMU_INBOUND_MSG0_RESET,
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IOPMU_INBOUND_MSG0_FLUSH,
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IOPMU_INBOUND_MSG0_SHUTDOWN,
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IOPMU_INBOUND_MSG0_STOP_BACKGROUND_TASK,
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IOPMU_INBOUND_MSG0_START_BACKGROUND_TASK,
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IOPMU_INBOUND_MSG0_RESET_COMM,
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IOPMU_INBOUND_MSG0_MAX = 0xff,
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/* iop-to-host messages */
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IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_0 = 0x100,
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IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_MAX = 0x1ff,
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IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_0 = 0x200,
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IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_MAX = 0x2ff,
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IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_0 = 0x300,
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IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_MAX = 0x3ff,
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};
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#define IOP_REQUEST_FLAG_SYNC_REQUEST 1
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#define IOP_REQUEST_FLAG_BIST_REQUEST 2
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#define IOP_REQUEST_FLAG_REMAPPED 4
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#define IOP_REQUEST_FLAG_OUTPUT_CONTEXT 8
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#define IOP_REQUEST_FLAG_ADDR_BITS 0x40 /* flags[31:16] is phy_addr[47:32] */
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enum hpt_iop_request_type {
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IOP_REQUEST_TYPE_GET_CONFIG = 0,
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IOP_REQUEST_TYPE_SET_CONFIG,
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IOP_REQUEST_TYPE_BLOCK_COMMAND,
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IOP_REQUEST_TYPE_SCSI_COMMAND,
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IOP_REQUEST_TYPE_IOCTL_COMMAND,
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IOP_REQUEST_TYPE_MAX
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};
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enum hpt_iop_result_type {
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IOP_RESULT_PENDING = 0,
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IOP_RESULT_SUCCESS,
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IOP_RESULT_FAIL,
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IOP_RESULT_BUSY,
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IOP_RESULT_RESET,
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IOP_RESULT_INVALID_REQUEST,
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IOP_RESULT_BAD_TARGET,
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IOP_RESULT_CHECK_CONDITION,
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};
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#pragma pack(1)
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struct hpt_iop_request_header {
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u_int32_t size;
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u_int32_t type;
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u_int32_t flags;
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u_int32_t result;
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u_int64_t context; /* host context */
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};
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struct hpt_iop_request_get_config {
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struct hpt_iop_request_header header;
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u_int32_t interface_version;
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u_int32_t firmware_version;
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u_int32_t max_requests;
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u_int32_t request_size;
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u_int32_t max_sg_count;
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u_int32_t data_transfer_length;
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u_int32_t alignment_mask;
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u_int32_t max_devices;
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u_int32_t sdram_size;
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};
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struct hpt_iop_request_set_config {
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struct hpt_iop_request_header header;
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u_int32_t iop_id;
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u_int16_t vbus_id;
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u_int16_t max_host_request_size;
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u_int32_t reserve[6];
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};
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struct hpt_iopsg {
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u_int32_t size;
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u_int32_t eot; /* non-zero: end of table */
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u_int64_t pci_address;
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};
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#define IOP_BLOCK_COMMAND_READ 1
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#define IOP_BLOCK_COMMAND_WRITE 2
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#define IOP_BLOCK_COMMAND_VERIFY 3
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#define IOP_BLOCK_COMMAND_FLUSH 4
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#define IOP_BLOCK_COMMAND_SHUTDOWN 5
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struct hpt_iop_request_block_command {
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struct hpt_iop_request_header header;
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u_int8_t channel;
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u_int8_t target;
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u_int8_t lun;
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u_int8_t pad1;
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u_int16_t command; /* IOP_BLOCK_COMMAND_{READ,WRITE} */
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u_int16_t sectors;
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u_int64_t lba;
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struct hpt_iopsg sg_list[1];
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};
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struct hpt_iop_request_scsi_command {
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struct hpt_iop_request_header header;
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u_int8_t channel;
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u_int8_t target;
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u_int8_t lun;
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u_int8_t pad1;
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u_int8_t cdb[16];
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u_int32_t dataxfer_length;
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struct hpt_iopsg sg_list[1];
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};
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struct hpt_iop_request_ioctl_command {
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struct hpt_iop_request_header header;
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u_int32_t ioctl_code;
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u_int32_t inbuf_size;
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u_int32_t outbuf_size;
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u_int32_t bytes_returned;
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u_int8_t buf[1];
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/* out data should be put at buf[(inbuf_size+3)&~3] */
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};
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struct hpt_iop_ioctl_param {
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u_int32_t Magic; /* used to check if it's a valid ioctl packet */
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u_int32_t dwIoControlCode; /* operation control code */
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unsigned long lpInBuffer; /* input data buffer */
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u_int32_t nInBufferSize; /* size of input data buffer */
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unsigned long lpOutBuffer; /* output data buffer */
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u_int32_t nOutBufferSize; /* size of output data buffer */
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unsigned long lpBytesReturned; /* count of HPT_U8s returned */
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} __packed;
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#define HPT_IOCTL_FLAG_OPEN 1
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#define HPT_CTL_CODE_BSD_TO_IOP(x) ((x)-0xff00)
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typedef struct cdev * ioctl_dev_t;
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typedef struct thread * ioctl_thread_t;
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struct hpt_iop_hba {
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struct hptiop_adapter_ops *ops;
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union {
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struct {
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struct hpt_iopmu_itl *mu;
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} itl;
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struct {
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struct hpt_iopmv_regs *regs;
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struct hpt_iopmu_mv *mu;
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} mv;
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struct {
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struct hpt_iop_request_get_config *config;
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struct hpt_iopmu_mvfrey *mu;
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int internal_mem_size;
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int list_count;
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struct mvfrey_inlist_entry *inlist;
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u_int64_t inlist_phy;
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u_int32_t inlist_wptr;
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struct mvfrey_outlist_entry *outlist;
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u_int64_t outlist_phy;
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u_int32_t *outlist_cptr; /* copy pointer shadow */
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u_int64_t outlist_cptr_phy;
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u_int32_t outlist_rptr;
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} mvfrey;
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} u;
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struct hpt_iop_hba *next;
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u_int32_t firmware_version;
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u_int32_t interface_version;
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u_int32_t max_devices;
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u_int32_t max_requests;
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u_int32_t max_request_size;
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u_int32_t max_sg_count;
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u_int32_t msg_done;
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device_t pcidev;
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u_int32_t pciunit;
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ioctl_dev_t ioctl_dev;
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bus_dma_tag_t parent_dmat;
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bus_dma_tag_t io_dmat;
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bus_dma_tag_t srb_dmat;
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bus_dma_tag_t ctlcfg_dmat;
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bus_dmamap_t srb_dmamap;
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bus_dmamap_t ctlcfg_dmamap;
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struct resource *bar0_res;
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bus_space_tag_t bar0t;
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bus_space_handle_t bar0h;
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int bar0_rid;
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struct resource *bar2_res;
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bus_space_tag_t bar2t;
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bus_space_handle_t bar2h;
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int bar2_rid;
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/* to release */
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u_int8_t *uncached_ptr;
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void *ctlcfg_ptr;
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/* for scsi request block */
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struct hpt_iop_srb *srb_list;
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/* for interrupt */
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struct resource *irq_res;
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void *irq_handle;
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/* for ioctl and set/get config */
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struct resource *ctlcfg_res;
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void *ctlcfg_handle;
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u_int64_t ctlcfgcmd_phy;
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u_int32_t config_done; /* can be negative value */
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u_int32_t initialized:1;
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/* other resources */
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struct cam_sim *sim;
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struct cam_path *path;
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void *req;
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struct mtx lock;
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#define HPT_IOCTL_FLAG_OPEN 1
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u_int32_t flag;
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struct hpt_iop_srb* srb[HPT_SRB_MAX_QUEUE_SIZE];
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};
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#pragma pack()
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enum hptiop_family {
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INTEL_BASED_IOP = 0,
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MV_BASED_IOP,
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MVFREY_BASED_IOP,
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UNKNOWN_BASED_IOP = 0xf
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};
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struct hptiop_adapter_ops {
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enum hptiop_family family;
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int (*iop_wait_ready)(struct hpt_iop_hba *hba, u_int32_t millisec);
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int (*internal_memalloc)(struct hpt_iop_hba *hba);
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int (*internal_memfree)(struct hpt_iop_hba *hba);
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int (*alloc_pci_res)(struct hpt_iop_hba *hba);
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void (*release_pci_res)(struct hpt_iop_hba *hba);
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void (*enable_intr)(struct hpt_iop_hba *hba);
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void (*disable_intr)(struct hpt_iop_hba *hba);
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int (*get_config)(struct hpt_iop_hba *hba,
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struct hpt_iop_request_get_config *config);
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int (*set_config)(struct hpt_iop_hba *hba,
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struct hpt_iop_request_set_config *config);
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int (*iop_intr)(struct hpt_iop_hba *hba);
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void (*post_msg)(struct hpt_iop_hba *hba, u_int32_t msg);
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void (*post_req)(struct hpt_iop_hba *hba, struct hpt_iop_srb *srb, bus_dma_segment_t *segs, int nsegs);
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int (*do_ioctl)(struct hpt_iop_hba *hba, struct hpt_iop_ioctl_param * pParams);
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int (*reset_comm)(struct hpt_iop_hba *hba);
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};
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struct hpt_iop_srb {
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u_int8_t req[HPT_SRB_MAX_REQ_SIZE];
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struct hpt_iop_hba *hba;
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union ccb *ccb;
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struct hpt_iop_srb *next;
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bus_dmamap_t dma_map;
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u_int64_t phy_addr;
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u_int32_t srb_flag;
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int index;
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struct callout_handle timeout_ch;
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};
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#define hptiop_lock_adapter(hba) mtx_lock(&(hba)->lock)
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#define hptiop_unlock_adapter(hba) mtx_unlock(&(hba)->lock)
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#define HPT_OSM_TIMEOUT (20*hz) /* timeout value for OS commands */
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#define HPT_DO_IOCONTROL _IOW('H', 0, struct hpt_iop_ioctl_param)
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#define HPT_SCAN_BUS _IO('H', 1)
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static __inline int hptiop_sleep(struct hpt_iop_hba *hba, void *ident,
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int priority, const char *wmesg, int timo)
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{
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int retval;
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retval = msleep(ident, &hba->lock, priority, wmesg, timo);
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return retval;
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}
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#define HPT_DEV_MAJOR 200
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#endif
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