daf9197cff
will sometimes fail to initialize problem due to a lock contention with management hardware. However, in order to deliver that fix it was necessary to take a shared code update as a whole, and this required scattered changes in the core code to be compatible. The em driver now has VLAN HW support added as the igb driver had previously. MFC after: ASAP - in time for 7.1 RELEASE
932 lines
23 KiB
C
932 lines
23 KiB
C
/******************************************************************************
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Copyright (c) 2001-2008, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#include "e1000_api.h"
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/**
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* e1000_init_nvm_ops_generic - Initialize NVM function pointers
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* @hw: pointer to the HW structure
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*
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* Setups up the function pointers to no-op functions
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**/
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void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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DEBUGFUNC("e1000_init_nvm_ops_generic");
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/* Initialize function pointers */
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nvm->ops.init_params = e1000_null_ops_generic;
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nvm->ops.acquire = e1000_null_ops_generic;
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nvm->ops.read = e1000_null_read_nvm;
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nvm->ops.release = e1000_null_nvm_generic;
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nvm->ops.reload = e1000_reload_nvm_generic;
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nvm->ops.update = e1000_null_ops_generic;
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nvm->ops.valid_led_default = e1000_null_led_default;
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nvm->ops.validate = e1000_null_ops_generic;
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nvm->ops.write = e1000_null_write_nvm;
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}
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/**
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* e1000_null_nvm_read - No-op function, return 0
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* @hw: pointer to the HW structure
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**/
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s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
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{
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DEBUGFUNC("e1000_null_read_nvm");
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return E1000_SUCCESS;
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}
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/**
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* e1000_null_nvm_generic - No-op function, return void
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* @hw: pointer to the HW structure
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**/
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void e1000_null_nvm_generic(struct e1000_hw *hw)
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{
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DEBUGFUNC("e1000_null_nvm_generic");
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return;
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}
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/**
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* e1000_null_led_default - No-op function, return 0
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* @hw: pointer to the HW structure
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**/
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s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
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{
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DEBUGFUNC("e1000_null_led_default");
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return E1000_SUCCESS;
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}
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/**
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* e1000_null_write_nvm - No-op function, return 0
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* @hw: pointer to the HW structure
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**/
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s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
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{
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DEBUGFUNC("e1000_null_write_nvm");
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return E1000_SUCCESS;
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}
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/**
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* e1000_raise_eec_clk - Raise EEPROM clock
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* @hw: pointer to the HW structure
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* @eecd: pointer to the EEPROM
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*
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* Enable/Raise the EEPROM clock bit.
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**/
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static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
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{
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*eecd = *eecd | E1000_EECD_SK;
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E1000_WRITE_REG(hw, E1000_EECD, *eecd);
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E1000_WRITE_FLUSH(hw);
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usec_delay(hw->nvm.delay_usec);
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}
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/**
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* e1000_lower_eec_clk - Lower EEPROM clock
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* @hw: pointer to the HW structure
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* @eecd: pointer to the EEPROM
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*
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* Clear/Lower the EEPROM clock bit.
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**/
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static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
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{
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*eecd = *eecd & ~E1000_EECD_SK;
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E1000_WRITE_REG(hw, E1000_EECD, *eecd);
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E1000_WRITE_FLUSH(hw);
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usec_delay(hw->nvm.delay_usec);
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}
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/**
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* e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
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* @hw: pointer to the HW structure
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* @data: data to send to the EEPROM
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* @count: number of bits to shift out
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*
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* We need to shift 'count' bits out to the EEPROM. So, the value in the
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* "data" parameter will be shifted out to the EEPROM one bit at a time.
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* In order to do this, "data" must be broken down into bits.
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**/
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static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 eecd = E1000_READ_REG(hw, E1000_EECD);
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u32 mask;
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DEBUGFUNC("e1000_shift_out_eec_bits");
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mask = 0x01 << (count - 1);
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if (nvm->type == e1000_nvm_eeprom_microwire)
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eecd &= ~E1000_EECD_DO;
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else
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if (nvm->type == e1000_nvm_eeprom_spi)
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eecd |= E1000_EECD_DO;
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do {
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eecd &= ~E1000_EECD_DI;
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if (data & mask)
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eecd |= E1000_EECD_DI;
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E1000_WRITE_REG(hw, E1000_EECD, eecd);
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E1000_WRITE_FLUSH(hw);
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usec_delay(nvm->delay_usec);
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e1000_raise_eec_clk(hw, &eecd);
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e1000_lower_eec_clk(hw, &eecd);
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mask >>= 1;
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} while (mask);
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eecd &= ~E1000_EECD_DI;
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E1000_WRITE_REG(hw, E1000_EECD, eecd);
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}
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/**
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* e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
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* @hw: pointer to the HW structure
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* @count: number of bits to shift in
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*
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* In order to read a register from the EEPROM, we need to shift 'count' bits
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* in from the EEPROM. Bits are "shifted in" by raising the clock input to
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* the EEPROM (setting the SK bit), and then reading the value of the data out
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* "DO" bit. During this "shifting in" process the data in "DI" bit should
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* always be clear.
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**/
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static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
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{
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u32 eecd;
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u32 i;
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u16 data;
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DEBUGFUNC("e1000_shift_in_eec_bits");
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eecd = E1000_READ_REG(hw, E1000_EECD);
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eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
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data = 0;
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for (i = 0; i < count; i++) {
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data <<= 1;
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e1000_raise_eec_clk(hw, &eecd);
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eecd = E1000_READ_REG(hw, E1000_EECD);
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eecd &= ~E1000_EECD_DI;
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if (eecd & E1000_EECD_DO)
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data |= 1;
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e1000_lower_eec_clk(hw, &eecd);
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}
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return data;
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}
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/**
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* e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
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* @hw: pointer to the HW structure
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* @ee_reg: EEPROM flag for polling
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*
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* Polls the EEPROM status bit for either read or write completion based
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* upon the value of 'ee_reg'.
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**/
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s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
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{
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u32 attempts = 100000;
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u32 i, reg = 0;
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s32 ret_val = -E1000_ERR_NVM;
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DEBUGFUNC("e1000_poll_eerd_eewr_done");
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for (i = 0; i < attempts; i++) {
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if (ee_reg == E1000_NVM_POLL_READ)
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reg = E1000_READ_REG(hw, E1000_EERD);
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else
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reg = E1000_READ_REG(hw, E1000_EEWR);
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if (reg & E1000_NVM_RW_REG_DONE) {
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ret_val = E1000_SUCCESS;
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break;
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}
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usec_delay(5);
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}
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return ret_val;
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}
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/**
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* e1000_acquire_nvm_generic - Generic request for access to EEPROM
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* @hw: pointer to the HW structure
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*
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* Set the EEPROM access request bit and wait for EEPROM access grant bit.
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* Return successful if access grant bit set, else clear the request for
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* EEPROM access and return -E1000_ERR_NVM (-1).
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**/
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s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
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{
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u32 eecd = E1000_READ_REG(hw, E1000_EECD);
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s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
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s32 ret_val = E1000_SUCCESS;
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DEBUGFUNC("e1000_acquire_nvm_generic");
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E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
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eecd = E1000_READ_REG(hw, E1000_EECD);
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while (timeout) {
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if (eecd & E1000_EECD_GNT)
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break;
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usec_delay(5);
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eecd = E1000_READ_REG(hw, E1000_EECD);
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timeout--;
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}
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if (!timeout) {
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eecd &= ~E1000_EECD_REQ;
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E1000_WRITE_REG(hw, E1000_EECD, eecd);
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DEBUGOUT("Could not acquire NVM grant\n");
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ret_val = -E1000_ERR_NVM;
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}
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return ret_val;
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}
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/**
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* e1000_standby_nvm - Return EEPROM to standby state
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* @hw: pointer to the HW structure
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*
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* Return the EEPROM to a standby state.
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**/
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static void e1000_standby_nvm(struct e1000_hw *hw)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 eecd = E1000_READ_REG(hw, E1000_EECD);
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DEBUGFUNC("e1000_standby_nvm");
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if (nvm->type == e1000_nvm_eeprom_microwire) {
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eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
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E1000_WRITE_REG(hw, E1000_EECD, eecd);
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E1000_WRITE_FLUSH(hw);
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usec_delay(nvm->delay_usec);
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e1000_raise_eec_clk(hw, &eecd);
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|
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/* Select EEPROM */
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eecd |= E1000_EECD_CS;
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E1000_WRITE_REG(hw, E1000_EECD, eecd);
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E1000_WRITE_FLUSH(hw);
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usec_delay(nvm->delay_usec);
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e1000_lower_eec_clk(hw, &eecd);
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} else
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if (nvm->type == e1000_nvm_eeprom_spi) {
|
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/* Toggle CS to flush commands */
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eecd |= E1000_EECD_CS;
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E1000_WRITE_REG(hw, E1000_EECD, eecd);
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E1000_WRITE_FLUSH(hw);
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usec_delay(nvm->delay_usec);
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eecd &= ~E1000_EECD_CS;
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E1000_WRITE_REG(hw, E1000_EECD, eecd);
|
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E1000_WRITE_FLUSH(hw);
|
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usec_delay(nvm->delay_usec);
|
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}
|
|
}
|
|
|
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/**
|
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* e1000_stop_nvm - Terminate EEPROM command
|
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* @hw: pointer to the HW structure
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*
|
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* Terminates the current command by inverting the EEPROM's chip select pin.
|
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**/
|
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void e1000_stop_nvm(struct e1000_hw *hw)
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{
|
|
u32 eecd;
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|
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DEBUGFUNC("e1000_stop_nvm");
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|
|
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eecd = E1000_READ_REG(hw, E1000_EECD);
|
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if (hw->nvm.type == e1000_nvm_eeprom_spi) {
|
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/* Pull CS high */
|
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eecd |= E1000_EECD_CS;
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e1000_lower_eec_clk(hw, &eecd);
|
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} else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
|
|
/* CS on Microwire is active-high */
|
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eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
|
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E1000_WRITE_REG(hw, E1000_EECD, eecd);
|
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e1000_raise_eec_clk(hw, &eecd);
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e1000_lower_eec_clk(hw, &eecd);
|
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}
|
|
}
|
|
|
|
/**
|
|
* e1000_release_nvm_generic - Release exclusive access to EEPROM
|
|
* @hw: pointer to the HW structure
|
|
*
|
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* Stop any current commands to the EEPROM and clear the EEPROM request bit.
|
|
**/
|
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void e1000_release_nvm_generic(struct e1000_hw *hw)
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|
{
|
|
u32 eecd;
|
|
|
|
DEBUGFUNC("e1000_release_nvm_generic");
|
|
|
|
e1000_stop_nvm(hw);
|
|
|
|
eecd = E1000_READ_REG(hw, E1000_EECD);
|
|
eecd &= ~E1000_EECD_REQ;
|
|
E1000_WRITE_REG(hw, E1000_EECD, eecd);
|
|
}
|
|
|
|
/**
|
|
* e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Setups the EEPROM for reading and writing.
|
|
**/
|
|
static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
|
|
{
|
|
struct e1000_nvm_info *nvm = &hw->nvm;
|
|
u32 eecd = E1000_READ_REG(hw, E1000_EECD);
|
|
s32 ret_val = E1000_SUCCESS;
|
|
u16 timeout = 0;
|
|
u8 spi_stat_reg;
|
|
|
|
DEBUGFUNC("e1000_ready_nvm_eeprom");
|
|
|
|
if (nvm->type == e1000_nvm_eeprom_microwire) {
|
|
/* Clear SK and DI */
|
|
eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
|
|
E1000_WRITE_REG(hw, E1000_EECD, eecd);
|
|
/* Set CS */
|
|
eecd |= E1000_EECD_CS;
|
|
E1000_WRITE_REG(hw, E1000_EECD, eecd);
|
|
} else
|
|
if (nvm->type == e1000_nvm_eeprom_spi) {
|
|
/* Clear SK and CS */
|
|
eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
|
|
E1000_WRITE_REG(hw, E1000_EECD, eecd);
|
|
usec_delay(1);
|
|
timeout = NVM_MAX_RETRY_SPI;
|
|
|
|
/*
|
|
* Read "Status Register" repeatedly until the LSB is cleared.
|
|
* The EEPROM will signal that the command has been completed
|
|
* by clearing bit 0 of the internal status register. If it's
|
|
* not cleared within 'timeout', then error out.
|
|
*/
|
|
while (timeout) {
|
|
e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
|
|
hw->nvm.opcode_bits);
|
|
spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
|
|
if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
|
|
break;
|
|
|
|
usec_delay(5);
|
|
e1000_standby_nvm(hw);
|
|
timeout--;
|
|
}
|
|
|
|
if (!timeout) {
|
|
DEBUGOUT("SPI NVM Status error\n");
|
|
ret_val = -E1000_ERR_NVM;
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000_read_nvm_spi - Read EEPROM's using SPI
|
|
* @hw: pointer to the HW structure
|
|
* @offset: offset of word in the EEPROM to read
|
|
* @words: number of words to read
|
|
* @data: word read from the EEPROM
|
|
*
|
|
* Reads a 16 bit word from the EEPROM.
|
|
**/
|
|
s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
|
|
{
|
|
struct e1000_nvm_info *nvm = &hw->nvm;
|
|
u32 i = 0;
|
|
s32 ret_val;
|
|
u16 word_in;
|
|
u8 read_opcode = NVM_READ_OPCODE_SPI;
|
|
|
|
DEBUGFUNC("e1000_read_nvm_spi");
|
|
|
|
/*
|
|
* A check for invalid values: offset too large, too many words,
|
|
* and not enough words.
|
|
*/
|
|
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
|
|
(words == 0)) {
|
|
DEBUGOUT("nvm parameter(s) out of bounds\n");
|
|
ret_val = -E1000_ERR_NVM;
|
|
goto out;
|
|
}
|
|
|
|
ret_val = nvm->ops.acquire(hw);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
ret_val = e1000_ready_nvm_eeprom(hw);
|
|
if (ret_val)
|
|
goto release;
|
|
|
|
e1000_standby_nvm(hw);
|
|
|
|
if ((nvm->address_bits == 8) && (offset >= 128))
|
|
read_opcode |= NVM_A8_OPCODE_SPI;
|
|
|
|
/* Send the READ command (opcode + addr) */
|
|
e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
|
|
e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
|
|
|
|
/*
|
|
* Read the data. SPI NVMs increment the address with each byte
|
|
* read and will roll over if reading beyond the end. This allows
|
|
* us to read the whole NVM from any offset
|
|
*/
|
|
for (i = 0; i < words; i++) {
|
|
word_in = e1000_shift_in_eec_bits(hw, 16);
|
|
data[i] = (word_in >> 8) | (word_in << 8);
|
|
}
|
|
|
|
release:
|
|
nvm->ops.release(hw);
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000_read_nvm_microwire - Reads EEPROM's using microwire
|
|
* @hw: pointer to the HW structure
|
|
* @offset: offset of word in the EEPROM to read
|
|
* @words: number of words to read
|
|
* @data: word read from the EEPROM
|
|
*
|
|
* Reads a 16 bit word from the EEPROM.
|
|
**/
|
|
s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
|
|
u16 *data)
|
|
{
|
|
struct e1000_nvm_info *nvm = &hw->nvm;
|
|
u32 i = 0;
|
|
s32 ret_val;
|
|
u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
|
|
|
|
DEBUGFUNC("e1000_read_nvm_microwire");
|
|
|
|
/*
|
|
* A check for invalid values: offset too large, too many words,
|
|
* and not enough words.
|
|
*/
|
|
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
|
|
(words == 0)) {
|
|
DEBUGOUT("nvm parameter(s) out of bounds\n");
|
|
ret_val = -E1000_ERR_NVM;
|
|
goto out;
|
|
}
|
|
|
|
ret_val = nvm->ops.acquire(hw);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
ret_val = e1000_ready_nvm_eeprom(hw);
|
|
if (ret_val)
|
|
goto release;
|
|
|
|
for (i = 0; i < words; i++) {
|
|
/* Send the READ command (opcode + addr) */
|
|
e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
|
|
e1000_shift_out_eec_bits(hw, (u16)(offset + i),
|
|
nvm->address_bits);
|
|
|
|
/*
|
|
* Read the data. For microwire, each word requires the
|
|
* overhead of setup and tear-down.
|
|
*/
|
|
data[i] = e1000_shift_in_eec_bits(hw, 16);
|
|
e1000_standby_nvm(hw);
|
|
}
|
|
|
|
release:
|
|
nvm->ops.release(hw);
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000_read_nvm_eerd - Reads EEPROM using EERD register
|
|
* @hw: pointer to the HW structure
|
|
* @offset: offset of word in the EEPROM to read
|
|
* @words: number of words to read
|
|
* @data: word read from the EEPROM
|
|
*
|
|
* Reads a 16 bit word from the EEPROM using the EERD register.
|
|
**/
|
|
s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
|
|
{
|
|
struct e1000_nvm_info *nvm = &hw->nvm;
|
|
u32 i, eerd = 0;
|
|
s32 ret_val = E1000_SUCCESS;
|
|
|
|
DEBUGFUNC("e1000_read_nvm_eerd");
|
|
|
|
/*
|
|
* A check for invalid values: offset too large, too many words,
|
|
* too many words for the offset, and not enough words.
|
|
*/
|
|
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
|
|
(words == 0)) {
|
|
DEBUGOUT("nvm parameter(s) out of bounds\n");
|
|
ret_val = -E1000_ERR_NVM;
|
|
goto out;
|
|
}
|
|
|
|
for (i = 0; i < words; i++) {
|
|
eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
|
|
E1000_NVM_RW_REG_START;
|
|
|
|
E1000_WRITE_REG(hw, E1000_EERD, eerd);
|
|
ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
|
|
if (ret_val)
|
|
break;
|
|
|
|
data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
|
|
E1000_NVM_RW_REG_DATA);
|
|
}
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000_write_nvm_spi - Write to EEPROM using SPI
|
|
* @hw: pointer to the HW structure
|
|
* @offset: offset within the EEPROM to be written to
|
|
* @words: number of words to write
|
|
* @data: 16 bit word(s) to be written to the EEPROM
|
|
*
|
|
* Writes data to EEPROM at offset using SPI interface.
|
|
*
|
|
* If e1000_update_nvm_checksum is not called after this function , the
|
|
* EEPROM will most likely contain an invalid checksum.
|
|
**/
|
|
s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
|
|
{
|
|
struct e1000_nvm_info *nvm = &hw->nvm;
|
|
s32 ret_val;
|
|
u16 widx = 0;
|
|
|
|
DEBUGFUNC("e1000_write_nvm_spi");
|
|
|
|
/*
|
|
* A check for invalid values: offset too large, too many words,
|
|
* and not enough words.
|
|
*/
|
|
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
|
|
(words == 0)) {
|
|
DEBUGOUT("nvm parameter(s) out of bounds\n");
|
|
ret_val = -E1000_ERR_NVM;
|
|
goto out;
|
|
}
|
|
|
|
ret_val = nvm->ops.acquire(hw);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
while (widx < words) {
|
|
u8 write_opcode = NVM_WRITE_OPCODE_SPI;
|
|
|
|
ret_val = e1000_ready_nvm_eeprom(hw);
|
|
if (ret_val)
|
|
goto release;
|
|
|
|
e1000_standby_nvm(hw);
|
|
|
|
/* Send the WRITE ENABLE command (8 bit opcode) */
|
|
e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
|
|
nvm->opcode_bits);
|
|
|
|
e1000_standby_nvm(hw);
|
|
|
|
/*
|
|
* Some SPI eeproms use the 8th address bit embedded in the
|
|
* opcode
|
|
*/
|
|
if ((nvm->address_bits == 8) && (offset >= 128))
|
|
write_opcode |= NVM_A8_OPCODE_SPI;
|
|
|
|
/* Send the Write command (8-bit opcode + addr) */
|
|
e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
|
|
e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
|
|
nvm->address_bits);
|
|
|
|
/* Loop to allow for up to whole page write of eeprom */
|
|
while (widx < words) {
|
|
u16 word_out = data[widx];
|
|
word_out = (word_out >> 8) | (word_out << 8);
|
|
e1000_shift_out_eec_bits(hw, word_out, 16);
|
|
widx++;
|
|
|
|
if ((((offset + widx) * 2) % nvm->page_size) == 0) {
|
|
e1000_standby_nvm(hw);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
msec_delay(10);
|
|
release:
|
|
nvm->ops.release(hw);
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000_write_nvm_microwire - Writes EEPROM using microwire
|
|
* @hw: pointer to the HW structure
|
|
* @offset: offset within the EEPROM to be written to
|
|
* @words: number of words to write
|
|
* @data: 16 bit word(s) to be written to the EEPROM
|
|
*
|
|
* Writes data to EEPROM at offset using microwire interface.
|
|
*
|
|
* If e1000_update_nvm_checksum is not called after this function , the
|
|
* EEPROM will most likely contain an invalid checksum.
|
|
**/
|
|
s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
|
|
u16 *data)
|
|
{
|
|
struct e1000_nvm_info *nvm = &hw->nvm;
|
|
s32 ret_val;
|
|
u32 eecd;
|
|
u16 words_written = 0;
|
|
u16 widx = 0;
|
|
|
|
DEBUGFUNC("e1000_write_nvm_microwire");
|
|
|
|
/*
|
|
* A check for invalid values: offset too large, too many words,
|
|
* and not enough words.
|
|
*/
|
|
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
|
|
(words == 0)) {
|
|
DEBUGOUT("nvm parameter(s) out of bounds\n");
|
|
ret_val = -E1000_ERR_NVM;
|
|
goto out;
|
|
}
|
|
|
|
ret_val = nvm->ops.acquire(hw);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
ret_val = e1000_ready_nvm_eeprom(hw);
|
|
if (ret_val)
|
|
goto release;
|
|
|
|
e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
|
|
(u16)(nvm->opcode_bits + 2));
|
|
|
|
e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
|
|
|
|
e1000_standby_nvm(hw);
|
|
|
|
while (words_written < words) {
|
|
e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
|
|
nvm->opcode_bits);
|
|
|
|
e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
|
|
nvm->address_bits);
|
|
|
|
e1000_shift_out_eec_bits(hw, data[words_written], 16);
|
|
|
|
e1000_standby_nvm(hw);
|
|
|
|
for (widx = 0; widx < 200; widx++) {
|
|
eecd = E1000_READ_REG(hw, E1000_EECD);
|
|
if (eecd & E1000_EECD_DO)
|
|
break;
|
|
usec_delay(50);
|
|
}
|
|
|
|
if (widx == 200) {
|
|
DEBUGOUT("NVM Write did not complete\n");
|
|
ret_val = -E1000_ERR_NVM;
|
|
goto release;
|
|
}
|
|
|
|
e1000_standby_nvm(hw);
|
|
|
|
words_written++;
|
|
}
|
|
|
|
e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
|
|
(u16)(nvm->opcode_bits + 2));
|
|
|
|
e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
|
|
|
|
release:
|
|
nvm->ops.release(hw);
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000_read_pba_num_generic - Read device part number
|
|
* @hw: pointer to the HW structure
|
|
* @pba_num: pointer to device part number
|
|
*
|
|
* Reads the product board assembly (PBA) number from the EEPROM and stores
|
|
* the value in pba_num.
|
|
**/
|
|
s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
|
|
{
|
|
s32 ret_val;
|
|
u16 nvm_data;
|
|
|
|
DEBUGFUNC("e1000_read_pba_num_generic");
|
|
|
|
ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
|
|
if (ret_val) {
|
|
DEBUGOUT("NVM Read Error\n");
|
|
goto out;
|
|
}
|
|
*pba_num = (u32)(nvm_data << 16);
|
|
|
|
ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
|
|
if (ret_val) {
|
|
DEBUGOUT("NVM Read Error\n");
|
|
goto out;
|
|
}
|
|
*pba_num |= nvm_data;
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000_read_mac_addr_generic - Read device MAC address
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Reads the device MAC address from the EEPROM and stores the value.
|
|
* Since devices with two ports use the same EEPROM, we increment the
|
|
* last bit in the MAC address for the second port.
|
|
**/
|
|
s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
|
|
{
|
|
s32 ret_val = E1000_SUCCESS;
|
|
u16 offset, nvm_data, i;
|
|
|
|
DEBUGFUNC("e1000_read_mac_addr");
|
|
|
|
for (i = 0; i < ETH_ADDR_LEN; i += 2) {
|
|
offset = i >> 1;
|
|
ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
|
|
if (ret_val) {
|
|
DEBUGOUT("NVM Read Error\n");
|
|
goto out;
|
|
}
|
|
hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
|
|
hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
|
|
}
|
|
|
|
/* Flip last bit of mac address if we're on second port */
|
|
if (hw->bus.func == E1000_FUNC_1)
|
|
hw->mac.perm_addr[5] ^= 1;
|
|
|
|
for (i = 0; i < ETH_ADDR_LEN; i++)
|
|
hw->mac.addr[i] = hw->mac.perm_addr[i];
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Calculates the EEPROM checksum by reading/adding each word of the EEPROM
|
|
* and then verifies that the sum of the EEPROM is equal to 0xBABA.
|
|
**/
|
|
s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
|
|
{
|
|
s32 ret_val = E1000_SUCCESS;
|
|
u16 checksum = 0;
|
|
u16 i, nvm_data;
|
|
|
|
DEBUGFUNC("e1000_validate_nvm_checksum_generic");
|
|
|
|
for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
|
|
ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
|
|
if (ret_val) {
|
|
DEBUGOUT("NVM Read Error\n");
|
|
goto out;
|
|
}
|
|
checksum += nvm_data;
|
|
}
|
|
|
|
if (checksum != (u16) NVM_SUM) {
|
|
DEBUGOUT("NVM Checksum Invalid\n");
|
|
ret_val = -E1000_ERR_NVM;
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000_update_nvm_checksum_generic - Update EEPROM checksum
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Updates the EEPROM checksum by reading/adding each word of the EEPROM
|
|
* up to the checksum. Then calculates the EEPROM checksum and writes the
|
|
* value to the EEPROM.
|
|
**/
|
|
s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
|
|
{
|
|
s32 ret_val;
|
|
u16 checksum = 0;
|
|
u16 i, nvm_data;
|
|
|
|
DEBUGFUNC("e1000_update_nvm_checksum");
|
|
|
|
for (i = 0; i < NVM_CHECKSUM_REG; i++) {
|
|
ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
|
|
if (ret_val) {
|
|
DEBUGOUT("NVM Read Error while updating checksum.\n");
|
|
goto out;
|
|
}
|
|
checksum += nvm_data;
|
|
}
|
|
checksum = (u16) NVM_SUM - checksum;
|
|
ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
|
|
if (ret_val)
|
|
DEBUGOUT("NVM Write Error while updating checksum.\n");
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000_reload_nvm_generic - Reloads EEPROM
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
|
|
* extended control register.
|
|
**/
|
|
void e1000_reload_nvm_generic(struct e1000_hw *hw)
|
|
{
|
|
u32 ctrl_ext;
|
|
|
|
DEBUGFUNC("e1000_reload_nvm_generic");
|
|
|
|
usec_delay(10);
|
|
ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
|
|
ctrl_ext |= E1000_CTRL_EXT_EE_RST;
|
|
E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
|
|
E1000_WRITE_FLUSH(hw);
|
|
}
|
|
|