227d67aa54
reduce lock congestion and improve SMP scalability of the SCSI/ATA stack, preparing the ground for the coming next GEOM direct dispatch support. Replace big per-SIM locks with bunch of smaller ones: - per-LUN locks to protect device and peripheral drivers state; - per-target locks to protect list of LUNs on target; - per-bus locks to protect reference counting; - per-send queue locks to protect queue of CCBs to be sent; - per-done queue locks to protect queue of completed CCBs; - remaining per-SIM locks now protect only HBA driver internals. While holding LUN lock it is allowed (while not recommended for performance reasons) to take SIM lock. The opposite acquisition order is forbidden. All the other locks are leaf locks, that can be taken anywhere, but should not be cascaded. Many functions, such as: xpt_action(), xpt_done(), xpt_async(), xpt_create_path(), etc. are no longer require (but allow) SIM lock to be held. To keep compatibility and solve cases where SIM lock can't be dropped, all xpt_async() calls in addition to xpt_done() calls are queued to completion threads for async processing in clean environment without SIM lock held. Instead of single CAM SWI thread, used for commands completion processing before, use multiple (depending on number of CPUs) threads. Load balanced between them using "hash" of the device B:T:L address. HBA drivers that can drop SIM lock during completion processing and have sufficient number of completion threads to efficiently scale to multiple CPUs can use new function xpt_done_direct() to avoid extra context switch. Make ahci(4) driver to use this mechanism depending on hardware setup. Sponsored by: iXsystems, Inc. MFC after: 2 months
1136 lines
30 KiB
C
1136 lines
30 KiB
C
/*-
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* Copyright (c) 2000 Matthew Jacob
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/errno.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/queue.h>
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#include <sys/sx.h>
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#include <sys/systm.h>
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#include <sys/sysctl.h>
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#include <sys/types.h>
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#include <cam/cam.h>
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#include <cam/cam_ccb.h>
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#include <cam/cam_periph.h>
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#include <cam/scsi/scsi_enc.h>
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#include <cam/scsi/scsi_enc_internal.h>
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#include <cam/scsi/scsi_message.h>
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/*
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* SAF-TE Type Device Emulation
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*/
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static int safte_set_enc_status(enc_softc_t *enc, uint8_t encstat, int slpflag);
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#define ALL_ENC_STAT (SES_ENCSTAT_CRITICAL | SES_ENCSTAT_UNRECOV | \
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SES_ENCSTAT_NONCRITICAL | SES_ENCSTAT_INFO)
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/*
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* SAF-TE specific defines- Mandatory ones only...
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*/
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/*
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* READ BUFFER ('get' commands) IDs- placed in offset 2 of cdb
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*/
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#define SAFTE_RD_RDCFG 0x00 /* read enclosure configuration */
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#define SAFTE_RD_RDESTS 0x01 /* read enclosure status */
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#define SAFTE_RD_RDDSTS 0x04 /* read drive slot status */
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#define SAFTE_RD_RDGFLG 0x05 /* read global flags */
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/*
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* WRITE BUFFER ('set' commands) IDs- placed in offset 0 of databuf
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*/
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#define SAFTE_WT_DSTAT 0x10 /* write device slot status */
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#define SAFTE_WT_SLTOP 0x12 /* perform slot operation */
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#define SAFTE_WT_FANSPD 0x13 /* set fan speed */
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#define SAFTE_WT_ACTPWS 0x14 /* turn on/off power supply */
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#define SAFTE_WT_GLOBAL 0x15 /* send global command */
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#define SAFT_SCRATCH 64
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#define SCSZ 0x8000
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typedef enum {
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SAFTE_UPDATE_NONE,
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SAFTE_UPDATE_READCONFIG,
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SAFTE_UPDATE_READGFLAGS,
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SAFTE_UPDATE_READENCSTATUS,
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SAFTE_UPDATE_READSLOTSTATUS,
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SAFTE_PROCESS_CONTROL_REQS,
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SAFTE_NUM_UPDATE_STATES
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} safte_update_action;
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static fsm_fill_handler_t safte_fill_read_buf_io;
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static fsm_fill_handler_t safte_fill_control_request;
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static fsm_done_handler_t safte_process_config;
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static fsm_done_handler_t safte_process_gflags;
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static fsm_done_handler_t safte_process_status;
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static fsm_done_handler_t safte_process_slotstatus;
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static fsm_done_handler_t safte_process_control_request;
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static struct enc_fsm_state enc_fsm_states[SAFTE_NUM_UPDATE_STATES] =
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{
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{ "SAFTE_UPDATE_NONE", 0, 0, 0, NULL, NULL, NULL },
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{
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"SAFTE_UPDATE_READCONFIG",
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SAFTE_RD_RDCFG,
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SAFT_SCRATCH,
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60 * 1000,
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safte_fill_read_buf_io,
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safte_process_config,
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enc_error
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},
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{
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"SAFTE_UPDATE_READGFLAGS",
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SAFTE_RD_RDGFLG,
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16,
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60 * 1000,
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safte_fill_read_buf_io,
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safte_process_gflags,
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enc_error
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},
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{
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"SAFTE_UPDATE_READENCSTATUS",
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SAFTE_RD_RDESTS,
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SCSZ,
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60 * 1000,
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safte_fill_read_buf_io,
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safte_process_status,
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enc_error
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},
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{
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"SAFTE_UPDATE_READSLOTSTATUS",
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SAFTE_RD_RDDSTS,
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SCSZ,
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60 * 1000,
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safte_fill_read_buf_io,
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safte_process_slotstatus,
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enc_error
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},
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{
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"SAFTE_PROCESS_CONTROL_REQS",
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0,
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SCSZ,
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60 * 1000,
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safte_fill_control_request,
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safte_process_control_request,
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enc_error
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}
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};
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typedef struct safte_control_request {
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int elm_idx;
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uint8_t elm_stat[4];
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int result;
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TAILQ_ENTRY(safte_control_request) links;
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} safte_control_request_t;
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TAILQ_HEAD(safte_control_reqlist, safte_control_request);
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typedef struct safte_control_reqlist safte_control_reqlist_t;
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enum {
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SES_SETSTATUS_ENC_IDX = -1
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};
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static void
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safte_terminate_control_requests(safte_control_reqlist_t *reqlist, int result)
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{
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safte_control_request_t *req;
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while ((req = TAILQ_FIRST(reqlist)) != NULL) {
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TAILQ_REMOVE(reqlist, req, links);
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req->result = result;
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wakeup(req);
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}
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}
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struct scfg {
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/*
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* Cached Configuration
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*/
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uint8_t Nfans; /* Number of Fans */
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uint8_t Npwr; /* Number of Power Supplies */
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uint8_t Nslots; /* Number of Device Slots */
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uint8_t DoorLock; /* Door Lock Installed */
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uint8_t Ntherm; /* Number of Temperature Sensors */
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uint8_t Nspkrs; /* Number of Speakers */
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uint8_t Ntstats; /* Number of Thermostats */
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/*
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* Cached Flag Bytes for Global Status
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*/
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uint8_t flag1;
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uint8_t flag2;
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/*
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* What object index ID is where various slots start.
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*/
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uint8_t pwroff;
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uint8_t slotoff;
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#define SAFT_ALARM_OFFSET(cc) (cc)->slotoff - 1
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encioc_enc_status_t adm_status;
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encioc_enc_status_t enc_status;
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encioc_enc_status_t slot_status;
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safte_control_reqlist_t requests;
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safte_control_request_t *current_request;
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int current_request_stage;
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int current_request_stages;
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};
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#define SAFT_FLG1_ALARM 0x1
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#define SAFT_FLG1_GLOBFAIL 0x2
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#define SAFT_FLG1_GLOBWARN 0x4
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#define SAFT_FLG1_ENCPWROFF 0x8
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#define SAFT_FLG1_ENCFANFAIL 0x10
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#define SAFT_FLG1_ENCPWRFAIL 0x20
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#define SAFT_FLG1_ENCDRVFAIL 0x40
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#define SAFT_FLG1_ENCDRVWARN 0x80
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#define SAFT_FLG2_LOCKDOOR 0x4
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#define SAFT_PRIVATE sizeof (struct scfg)
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static char *safte_2little = "Too Little Data Returned (%d) at line %d\n";
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#define SAFT_BAIL(r, x) \
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if ((r) >= (x)) { \
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ENC_VLOG(enc, safte_2little, x, __LINE__);\
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return (EIO); \
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}
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int emulate_array_devices = 1;
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SYSCTL_DECL(_kern_cam_enc);
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SYSCTL_INT(_kern_cam_enc, OID_AUTO, emulate_array_devices, CTLFLAG_RW,
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&emulate_array_devices, 0, "Emulate Array Devices for SAF-TE");
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TUNABLE_INT("kern.cam.enc.emulate_array_devices", &emulate_array_devices);
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static int
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safte_fill_read_buf_io(enc_softc_t *enc, struct enc_fsm_state *state,
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union ccb *ccb, uint8_t *buf)
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{
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if (state->page_code != SAFTE_RD_RDCFG &&
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enc->enc_cache.nelms == 0) {
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enc_update_request(enc, SAFTE_UPDATE_READCONFIG);
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return (-1);
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}
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if (enc->enc_type == ENC_SEMB_SAFT) {
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semb_read_buffer(&ccb->ataio, /*retries*/5,
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NULL, MSG_SIMPLE_Q_TAG,
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state->page_code, buf, state->buf_size,
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state->timeout);
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} else {
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scsi_read_buffer(&ccb->csio, /*retries*/5,
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NULL, MSG_SIMPLE_Q_TAG, 1,
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state->page_code, 0, buf, state->buf_size,
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SSD_FULL_SIZE, state->timeout);
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}
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return (0);
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}
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static int
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safte_process_config(enc_softc_t *enc, struct enc_fsm_state *state,
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union ccb *ccb, uint8_t **bufp, int error, int xfer_len)
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{
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struct scfg *cfg;
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uint8_t *buf = *bufp;
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int i, r;
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cfg = enc->enc_private;
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if (cfg == NULL)
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return (ENXIO);
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if (error != 0)
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return (error);
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if (xfer_len < 6) {
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ENC_VLOG(enc, "too little data (%d) for configuration\n",
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xfer_len);
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return (EIO);
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}
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cfg->Nfans = buf[0];
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cfg->Npwr = buf[1];
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cfg->Nslots = buf[2];
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cfg->DoorLock = buf[3];
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cfg->Ntherm = buf[4];
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cfg->Nspkrs = buf[5];
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if (xfer_len >= 7)
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cfg->Ntstats = buf[6] & 0x0f;
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else
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cfg->Ntstats = 0;
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ENC_VLOG(enc, "Nfans %d Npwr %d Nslots %d Lck %d Ntherm %d Nspkrs %d "
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"Ntstats %d\n",
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cfg->Nfans, cfg->Npwr, cfg->Nslots, cfg->DoorLock, cfg->Ntherm,
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cfg->Nspkrs, cfg->Ntstats);
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enc->enc_cache.nelms = cfg->Nfans + cfg->Npwr + cfg->Nslots +
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cfg->DoorLock + cfg->Ntherm + cfg->Nspkrs + cfg->Ntstats + 1;
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ENC_FREE_AND_NULL(enc->enc_cache.elm_map);
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enc->enc_cache.elm_map =
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ENC_MALLOCZ(enc->enc_cache.nelms * sizeof(enc_element_t));
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if (enc->enc_cache.elm_map == NULL) {
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enc->enc_cache.nelms = 0;
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return (ENOMEM);
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}
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|
r = 0;
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/*
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* Note that this is all arranged for the convenience
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* in later fetches of status.
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*/
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for (i = 0; i < cfg->Nfans; i++)
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enc->enc_cache.elm_map[r++].enctype = ELMTYP_FAN;
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cfg->pwroff = (uint8_t) r;
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for (i = 0; i < cfg->Npwr; i++)
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enc->enc_cache.elm_map[r++].enctype = ELMTYP_POWER;
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for (i = 0; i < cfg->DoorLock; i++)
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enc->enc_cache.elm_map[r++].enctype = ELMTYP_DOORLOCK;
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if (cfg->Nspkrs > 0)
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enc->enc_cache.elm_map[r++].enctype = ELMTYP_ALARM;
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for (i = 0; i < cfg->Ntherm; i++)
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enc->enc_cache.elm_map[r++].enctype = ELMTYP_THERM;
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for (i = 0; i <= cfg->Ntstats; i++)
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enc->enc_cache.elm_map[r++].enctype = ELMTYP_THERM;
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cfg->slotoff = (uint8_t) r;
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for (i = 0; i < cfg->Nslots; i++)
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enc->enc_cache.elm_map[r++].enctype =
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emulate_array_devices ? ELMTYP_ARRAY_DEV :
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ELMTYP_DEVICE;
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enc_update_request(enc, SAFTE_UPDATE_READGFLAGS);
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enc_update_request(enc, SAFTE_UPDATE_READENCSTATUS);
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enc_update_request(enc, SAFTE_UPDATE_READSLOTSTATUS);
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return (0);
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}
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|
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static int
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safte_process_gflags(enc_softc_t *enc, struct enc_fsm_state *state,
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union ccb *ccb, uint8_t **bufp, int error, int xfer_len)
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{
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struct scfg *cfg;
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uint8_t *buf = *bufp;
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cfg = enc->enc_private;
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if (cfg == NULL)
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return (ENXIO);
|
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if (error != 0)
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return (error);
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SAFT_BAIL(3, xfer_len);
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cfg->flag1 = buf[1];
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cfg->flag2 = buf[2];
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cfg->adm_status = 0;
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if (cfg->flag1 & SAFT_FLG1_GLOBFAIL)
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cfg->adm_status |= SES_ENCSTAT_CRITICAL;
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else if (cfg->flag1 & SAFT_FLG1_GLOBWARN)
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cfg->adm_status |= SES_ENCSTAT_NONCRITICAL;
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|
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return (0);
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}
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|
|
|
static int
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safte_process_status(enc_softc_t *enc, struct enc_fsm_state *state,
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union ccb *ccb, uint8_t **bufp, int error, int xfer_len)
|
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{
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|
struct scfg *cfg;
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uint8_t *buf = *bufp;
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int oid, r, i, nitems;
|
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uint16_t tempflags;
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enc_cache_t *cache = &enc->enc_cache;
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|
|
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cfg = enc->enc_private;
|
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if (cfg == NULL)
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return (ENXIO);
|
|
if (error != 0)
|
|
return (error);
|
|
|
|
oid = r = 0;
|
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cfg->enc_status = 0;
|
|
|
|
for (nitems = i = 0; i < cfg->Nfans; i++) {
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SAFT_BAIL(r, xfer_len);
|
|
/*
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* 0 = Fan Operational
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|
* 1 = Fan is malfunctioning
|
|
* 2 = Fan is not present
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|
* 0x80 = Unknown or Not Reportable Status
|
|
*/
|
|
cache->elm_map[oid].encstat[1] = 0; /* resvd */
|
|
cache->elm_map[oid].encstat[2] = 0; /* resvd */
|
|
if (cfg->flag1 & SAFT_FLG1_ENCFANFAIL)
|
|
cache->elm_map[oid].encstat[3] |= 0x40;
|
|
else
|
|
cache->elm_map[oid].encstat[3] &= ~0x40;
|
|
switch ((int)buf[r]) {
|
|
case 0:
|
|
nitems++;
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_OK;
|
|
if ((cache->elm_map[oid].encstat[3] & 0x37) == 0)
|
|
cache->elm_map[oid].encstat[3] |= 0x27;
|
|
break;
|
|
|
|
case 1:
|
|
cache->elm_map[oid].encstat[0] =
|
|
SES_OBJSTAT_CRIT;
|
|
/*
|
|
* FAIL and FAN STOPPED synthesized
|
|
*/
|
|
cache->elm_map[oid].encstat[3] |= 0x10;
|
|
cache->elm_map[oid].encstat[3] &= ~0x07;
|
|
/*
|
|
* Enclosure marked with CRITICAL error
|
|
* if only one fan or no thermometers,
|
|
* else the NONCRITICAL error is set.
|
|
*/
|
|
if (cfg->Nfans == 1 || (cfg->Ntherm + cfg->Ntstats) == 0)
|
|
cfg->enc_status |= SES_ENCSTAT_CRITICAL;
|
|
else
|
|
cfg->enc_status |= SES_ENCSTAT_NONCRITICAL;
|
|
break;
|
|
case 2:
|
|
cache->elm_map[oid].encstat[0] =
|
|
SES_OBJSTAT_NOTINSTALLED;
|
|
cache->elm_map[oid].encstat[3] |= 0x10;
|
|
cache->elm_map[oid].encstat[3] &= ~0x07;
|
|
/*
|
|
* Enclosure marked with CRITICAL error
|
|
* if only one fan or no thermometers,
|
|
* else the NONCRITICAL error is set.
|
|
*/
|
|
if (cfg->Nfans == 1)
|
|
cfg->enc_status |= SES_ENCSTAT_CRITICAL;
|
|
else
|
|
cfg->enc_status |= SES_ENCSTAT_NONCRITICAL;
|
|
break;
|
|
case 0x80:
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_UNKNOWN;
|
|
cache->elm_map[oid].encstat[3] = 0;
|
|
cfg->enc_status |= SES_ENCSTAT_INFO;
|
|
break;
|
|
default:
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_UNSUPPORTED;
|
|
ENC_VLOG(enc, "Unknown fan%d status 0x%x\n", i,
|
|
buf[r] & 0xff);
|
|
break;
|
|
}
|
|
cache->elm_map[oid++].svalid = 1;
|
|
r++;
|
|
}
|
|
|
|
/*
|
|
* No matter how you cut it, no cooling elements when there
|
|
* should be some there is critical.
|
|
*/
|
|
if (cfg->Nfans && nitems == 0)
|
|
cfg->enc_status |= SES_ENCSTAT_CRITICAL;
|
|
|
|
for (i = 0; i < cfg->Npwr; i++) {
|
|
SAFT_BAIL(r, xfer_len);
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_UNKNOWN;
|
|
cache->elm_map[oid].encstat[1] = 0; /* resvd */
|
|
cache->elm_map[oid].encstat[2] = 0; /* resvd */
|
|
cache->elm_map[oid].encstat[3] = 0x20; /* requested on */
|
|
switch (buf[r]) {
|
|
case 0x00: /* pws operational and on */
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_OK;
|
|
break;
|
|
case 0x01: /* pws operational and off */
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_OK;
|
|
cache->elm_map[oid].encstat[3] = 0x10;
|
|
cfg->enc_status |= SES_ENCSTAT_INFO;
|
|
break;
|
|
case 0x10: /* pws is malfunctioning and commanded on */
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_CRIT;
|
|
cache->elm_map[oid].encstat[3] = 0x61;
|
|
cfg->enc_status |= SES_ENCSTAT_NONCRITICAL;
|
|
break;
|
|
|
|
case 0x11: /* pws is malfunctioning and commanded off */
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_NONCRIT;
|
|
cache->elm_map[oid].encstat[3] = 0x51;
|
|
cfg->enc_status |= SES_ENCSTAT_NONCRITICAL;
|
|
break;
|
|
case 0x20: /* pws is not present */
|
|
cache->elm_map[oid].encstat[0] =
|
|
SES_OBJSTAT_NOTINSTALLED;
|
|
cache->elm_map[oid].encstat[3] = 0;
|
|
cfg->enc_status |= SES_ENCSTAT_INFO;
|
|
break;
|
|
case 0x21: /* pws is present */
|
|
/*
|
|
* This is for enclosures that cannot tell whether the
|
|
* device is on or malfunctioning, but know that it is
|
|
* present. Just fall through.
|
|
*/
|
|
/* FALLTHROUGH */
|
|
case 0x80: /* Unknown or Not Reportable Status */
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_UNKNOWN;
|
|
cache->elm_map[oid].encstat[3] = 0;
|
|
cfg->enc_status |= SES_ENCSTAT_INFO;
|
|
break;
|
|
default:
|
|
ENC_VLOG(enc, "unknown power supply %d status (0x%x)\n",
|
|
i, buf[r] & 0xff);
|
|
break;
|
|
}
|
|
enc->enc_cache.elm_map[oid++].svalid = 1;
|
|
r++;
|
|
}
|
|
|
|
/*
|
|
* Copy Slot SCSI IDs
|
|
*/
|
|
for (i = 0; i < cfg->Nslots; i++) {
|
|
SAFT_BAIL(r, xfer_len);
|
|
if (cache->elm_map[cfg->slotoff + i].enctype == ELMTYP_DEVICE)
|
|
cache->elm_map[cfg->slotoff + i].encstat[1] = buf[r];
|
|
r++;
|
|
}
|
|
|
|
/*
|
|
* We always have doorlock status, no matter what,
|
|
* but we only save the status if we have one.
|
|
*/
|
|
SAFT_BAIL(r, xfer_len);
|
|
if (cfg->DoorLock) {
|
|
/*
|
|
* 0 = Door Locked
|
|
* 1 = Door Unlocked, or no Lock Installed
|
|
* 0x80 = Unknown or Not Reportable Status
|
|
*/
|
|
cache->elm_map[oid].encstat[1] = 0;
|
|
cache->elm_map[oid].encstat[2] = 0;
|
|
switch (buf[r]) {
|
|
case 0:
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_OK;
|
|
cache->elm_map[oid].encstat[3] = 0;
|
|
break;
|
|
case 1:
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_OK;
|
|
cache->elm_map[oid].encstat[3] = 1;
|
|
break;
|
|
case 0x80:
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_UNKNOWN;
|
|
cache->elm_map[oid].encstat[3] = 0;
|
|
cfg->enc_status |= SES_ENCSTAT_INFO;
|
|
break;
|
|
default:
|
|
cache->elm_map[oid].encstat[0] =
|
|
SES_OBJSTAT_UNSUPPORTED;
|
|
ENC_VLOG(enc, "unknown lock status 0x%x\n",
|
|
buf[r] & 0xff);
|
|
break;
|
|
}
|
|
cache->elm_map[oid++].svalid = 1;
|
|
}
|
|
r++;
|
|
|
|
/*
|
|
* We always have speaker status, no matter what,
|
|
* but we only save the status if we have one.
|
|
*/
|
|
SAFT_BAIL(r, xfer_len);
|
|
if (cfg->Nspkrs) {
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_OK;
|
|
cache->elm_map[oid].encstat[1] = 0;
|
|
cache->elm_map[oid].encstat[2] = 0;
|
|
if (buf[r] == 0) {
|
|
cache->elm_map[oid].encstat[0] |= SESCTL_DISABLE;
|
|
cache->elm_map[oid].encstat[3] |= 0x40;
|
|
}
|
|
cache->elm_map[oid++].svalid = 1;
|
|
}
|
|
r++;
|
|
|
|
/*
|
|
* Now, for "pseudo" thermometers, we have two bytes
|
|
* of information in enclosure status- 16 bits. Actually,
|
|
* the MSB is a single TEMP ALERT flag indicating whether
|
|
* any other bits are set, but, thanks to fuzzy thinking,
|
|
* in the SAF-TE spec, this can also be set even if no
|
|
* other bits are set, thus making this really another
|
|
* binary temperature sensor.
|
|
*/
|
|
|
|
SAFT_BAIL(r + cfg->Ntherm, xfer_len);
|
|
tempflags = buf[r + cfg->Ntherm];
|
|
SAFT_BAIL(r + cfg->Ntherm + 1, xfer_len);
|
|
tempflags |= (tempflags << 8) | buf[r + cfg->Ntherm + 1];
|
|
|
|
for (i = 0; i < cfg->Ntherm; i++) {
|
|
SAFT_BAIL(r, xfer_len);
|
|
/*
|
|
* Status is a range from -10 to 245 deg Celsius,
|
|
* which we need to normalize to -20 to -245 according
|
|
* to the latest SCSI spec, which makes little
|
|
* sense since this would overflow an 8bit value.
|
|
* Well, still, the base normalization is -20,
|
|
* not -10, so we have to adjust.
|
|
*
|
|
* So what's over and under temperature?
|
|
* Hmm- we'll state that 'normal' operating
|
|
* is 10 to 40 deg Celsius.
|
|
*/
|
|
|
|
/*
|
|
* Actually.... All of the units that people out in the world
|
|
* seem to have do not come even close to setting a value that
|
|
* complies with this spec.
|
|
*
|
|
* The closest explanation I could find was in an
|
|
* LSI-Logic manual, which seemed to indicate that
|
|
* this value would be set by whatever the I2C code
|
|
* would interpolate from the output of an LM75
|
|
* temperature sensor.
|
|
*
|
|
* This means that it is impossible to use the actual
|
|
* numeric value to predict anything. But we don't want
|
|
* to lose the value. So, we'll propagate the *uncorrected*
|
|
* value and set SES_OBJSTAT_NOTAVAIL. We'll depend on the
|
|
* temperature flags for warnings.
|
|
*/
|
|
if (tempflags & (1 << i)) {
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_CRIT;
|
|
cfg->enc_status |= SES_ENCSTAT_CRITICAL;
|
|
} else
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_OK;
|
|
cache->elm_map[oid].encstat[1] = 0;
|
|
cache->elm_map[oid].encstat[2] = buf[r];
|
|
cache->elm_map[oid].encstat[3] = 0;
|
|
cache->elm_map[oid++].svalid = 1;
|
|
r++;
|
|
}
|
|
|
|
for (i = 0; i <= cfg->Ntstats; i++) {
|
|
cache->elm_map[oid].encstat[1] = 0;
|
|
if (tempflags & (1 <<
|
|
((i == cfg->Ntstats) ? 15 : (cfg->Ntherm + i)))) {
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_CRIT;
|
|
cache->elm_map[4].encstat[2] = 0xff;
|
|
/*
|
|
* Set 'over temperature' failure.
|
|
*/
|
|
cache->elm_map[oid].encstat[3] = 8;
|
|
cfg->enc_status |= SES_ENCSTAT_CRITICAL;
|
|
} else {
|
|
/*
|
|
* We used to say 'not available' and synthesize a
|
|
* nominal 30 deg (C)- that was wrong. Actually,
|
|
* Just say 'OK', and use the reserved value of
|
|
* zero.
|
|
*/
|
|
if ((cfg->Ntherm + cfg->Ntstats) == 0)
|
|
cache->elm_map[oid].encstat[0] =
|
|
SES_OBJSTAT_NOTAVAIL;
|
|
else
|
|
cache->elm_map[oid].encstat[0] =
|
|
SES_OBJSTAT_OK;
|
|
cache->elm_map[oid].encstat[2] = 0;
|
|
cache->elm_map[oid].encstat[3] = 0;
|
|
}
|
|
cache->elm_map[oid++].svalid = 1;
|
|
}
|
|
r += 2;
|
|
|
|
cache->enc_status =
|
|
cfg->enc_status | cfg->slot_status | cfg->adm_status;
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
safte_process_slotstatus(enc_softc_t *enc, struct enc_fsm_state *state,
|
|
union ccb *ccb, uint8_t **bufp, int error, int xfer_len)
|
|
{
|
|
struct scfg *cfg;
|
|
uint8_t *buf = *bufp;
|
|
enc_cache_t *cache = &enc->enc_cache;
|
|
int oid, r, i;
|
|
|
|
cfg = enc->enc_private;
|
|
if (cfg == NULL)
|
|
return (ENXIO);
|
|
if (error != 0)
|
|
return (error);
|
|
cfg->slot_status = 0;
|
|
oid = cfg->slotoff;
|
|
for (r = i = 0; i < cfg->Nslots; i++, r += 4) {
|
|
SAFT_BAIL(r+3, xfer_len);
|
|
if (cache->elm_map[oid].enctype == ELMTYP_ARRAY_DEV)
|
|
cache->elm_map[oid].encstat[1] = 0;
|
|
cache->elm_map[oid].encstat[2] &= SESCTL_RQSID;
|
|
cache->elm_map[oid].encstat[3] = 0;
|
|
if ((buf[r+3] & 0x01) == 0) { /* no device */
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_NOTINSTALLED;
|
|
} else if (buf[r+0] & 0x02) {
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_CRIT;
|
|
cfg->slot_status |= SES_ENCSTAT_CRITICAL;
|
|
} else if (buf[r+0] & 0x40) {
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_NONCRIT;
|
|
cfg->slot_status |= SES_ENCSTAT_NONCRITICAL;
|
|
} else {
|
|
cache->elm_map[oid].encstat[0] = SES_OBJSTAT_OK;
|
|
}
|
|
if (buf[r+3] & 0x2) {
|
|
if (buf[r+3] & 0x01)
|
|
cache->elm_map[oid].encstat[2] |= SESCTL_RQSRMV;
|
|
else
|
|
cache->elm_map[oid].encstat[2] |= SESCTL_RQSINS;
|
|
}
|
|
if ((buf[r+3] & 0x04) == 0)
|
|
cache->elm_map[oid].encstat[3] |= SESCTL_DEVOFF;
|
|
if (buf[r+0] & 0x02)
|
|
cache->elm_map[oid].encstat[3] |= SESCTL_RQSFLT;
|
|
if (buf[r+0] & 0x40)
|
|
cache->elm_map[oid].encstat[0] |= SESCTL_PRDFAIL;
|
|
if (cache->elm_map[oid].enctype == ELMTYP_ARRAY_DEV) {
|
|
if (buf[r+0] & 0x01)
|
|
cache->elm_map[oid].encstat[1] |= 0x80;
|
|
if (buf[r+0] & 0x04)
|
|
cache->elm_map[oid].encstat[1] |= 0x02;
|
|
if (buf[r+0] & 0x08)
|
|
cache->elm_map[oid].encstat[1] |= 0x04;
|
|
if (buf[r+0] & 0x10)
|
|
cache->elm_map[oid].encstat[1] |= 0x08;
|
|
if (buf[r+0] & 0x20)
|
|
cache->elm_map[oid].encstat[1] |= 0x10;
|
|
if (buf[r+1] & 0x01)
|
|
cache->elm_map[oid].encstat[1] |= 0x20;
|
|
if (buf[r+1] & 0x02)
|
|
cache->elm_map[oid].encstat[1] |= 0x01;
|
|
}
|
|
cache->elm_map[oid++].svalid = 1;
|
|
}
|
|
|
|
cache->enc_status =
|
|
cfg->enc_status | cfg->slot_status | cfg->adm_status;
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
safte_fill_control_request(enc_softc_t *enc, struct enc_fsm_state *state,
|
|
union ccb *ccb, uint8_t *buf)
|
|
{
|
|
struct scfg *cfg;
|
|
enc_element_t *ep, *ep1;
|
|
safte_control_request_t *req;
|
|
int i, idx, xfer_len;
|
|
|
|
cfg = enc->enc_private;
|
|
if (cfg == NULL)
|
|
return (ENXIO);
|
|
|
|
if (enc->enc_cache.nelms == 0) {
|
|
enc_update_request(enc, SAFTE_UPDATE_READCONFIG);
|
|
return (-1);
|
|
}
|
|
|
|
if (cfg->current_request == NULL) {
|
|
cfg->current_request = TAILQ_FIRST(&cfg->requests);
|
|
TAILQ_REMOVE(&cfg->requests, cfg->current_request, links);
|
|
cfg->current_request_stage = 0;
|
|
cfg->current_request_stages = 1;
|
|
}
|
|
req = cfg->current_request;
|
|
|
|
idx = (int)req->elm_idx;
|
|
if (req->elm_idx == SES_SETSTATUS_ENC_IDX) {
|
|
cfg->adm_status = req->elm_stat[0] & ALL_ENC_STAT;
|
|
cfg->flag1 &= ~(SAFT_FLG1_GLOBFAIL|SAFT_FLG1_GLOBWARN);
|
|
if (req->elm_stat[0] & (SES_ENCSTAT_CRITICAL|SES_ENCSTAT_UNRECOV))
|
|
cfg->flag1 |= SAFT_FLG1_GLOBFAIL;
|
|
else if (req->elm_stat[0] & SES_ENCSTAT_NONCRITICAL)
|
|
cfg->flag1 |= SAFT_FLG1_GLOBWARN;
|
|
buf[0] = SAFTE_WT_GLOBAL;
|
|
buf[1] = cfg->flag1;
|
|
buf[2] = cfg->flag2;
|
|
buf[3] = 0;
|
|
xfer_len = 16;
|
|
} else {
|
|
ep = &enc->enc_cache.elm_map[idx];
|
|
|
|
switch (ep->enctype) {
|
|
case ELMTYP_DEVICE:
|
|
case ELMTYP_ARRAY_DEV:
|
|
switch (cfg->current_request_stage) {
|
|
case 0:
|
|
ep->priv = 0;
|
|
if (req->elm_stat[0] & SESCTL_PRDFAIL)
|
|
ep->priv |= 0x40;
|
|
if (req->elm_stat[3] & SESCTL_RQSFLT)
|
|
ep->priv |= 0x02;
|
|
if (ep->enctype == ELMTYP_ARRAY_DEV) {
|
|
if (req->elm_stat[1] & 0x01)
|
|
ep->priv |= 0x200;
|
|
if (req->elm_stat[1] & 0x02)
|
|
ep->priv |= 0x04;
|
|
if (req->elm_stat[1] & 0x04)
|
|
ep->priv |= 0x08;
|
|
if (req->elm_stat[1] & 0x08)
|
|
ep->priv |= 0x10;
|
|
if (req->elm_stat[1] & 0x10)
|
|
ep->priv |= 0x20;
|
|
if (req->elm_stat[1] & 0x20)
|
|
ep->priv |= 0x100;
|
|
if (req->elm_stat[1] & 0x80)
|
|
ep->priv |= 0x01;
|
|
}
|
|
if (ep->priv == 0)
|
|
ep->priv |= 0x01; /* no errors */
|
|
|
|
buf[0] = SAFTE_WT_DSTAT;
|
|
for (i = 0; i < cfg->Nslots; i++) {
|
|
ep1 = &enc->enc_cache.elm_map[cfg->slotoff + i];
|
|
buf[1 + (3 * i)] = ep1->priv;
|
|
buf[2 + (3 * i)] = ep1->priv >> 8;
|
|
}
|
|
xfer_len = cfg->Nslots * 3 + 1;
|
|
#define DEVON(x) (!(((x)[2] & SESCTL_RQSINS) | \
|
|
((x)[2] & SESCTL_RQSRMV) | \
|
|
((x)[3] & SESCTL_DEVOFF)))
|
|
if (DEVON(req->elm_stat) != DEVON(ep->encstat))
|
|
cfg->current_request_stages++;
|
|
#define IDON(x) (!!((x)[2] & SESCTL_RQSID))
|
|
if (IDON(req->elm_stat) != IDON(ep->encstat))
|
|
cfg->current_request_stages++;
|
|
break;
|
|
case 1:
|
|
case 2:
|
|
buf[0] = SAFTE_WT_SLTOP;
|
|
buf[1] = idx - cfg->slotoff;
|
|
if (cfg->current_request_stage == 1 &&
|
|
DEVON(req->elm_stat) != DEVON(ep->encstat)) {
|
|
if (DEVON(req->elm_stat))
|
|
buf[2] = 0x01;
|
|
else
|
|
buf[2] = 0x02;
|
|
} else {
|
|
if (IDON(req->elm_stat))
|
|
buf[2] = 0x04;
|
|
else
|
|
buf[2] = 0x00;
|
|
ep->encstat[2] &= ~SESCTL_RQSID;
|
|
ep->encstat[2] |= req->elm_stat[2] &
|
|
SESCTL_RQSID;
|
|
}
|
|
xfer_len = 64;
|
|
break;
|
|
default:
|
|
return (EINVAL);
|
|
}
|
|
break;
|
|
case ELMTYP_POWER:
|
|
cfg->current_request_stages = 2;
|
|
switch (cfg->current_request_stage) {
|
|
case 0:
|
|
if (req->elm_stat[3] & SESCTL_RQSTFAIL) {
|
|
cfg->flag1 |= SAFT_FLG1_ENCPWRFAIL;
|
|
} else {
|
|
cfg->flag1 &= ~SAFT_FLG1_ENCPWRFAIL;
|
|
}
|
|
buf[0] = SAFTE_WT_GLOBAL;
|
|
buf[1] = cfg->flag1;
|
|
buf[2] = cfg->flag2;
|
|
buf[3] = 0;
|
|
xfer_len = 16;
|
|
break;
|
|
case 1:
|
|
buf[0] = SAFTE_WT_ACTPWS;
|
|
buf[1] = idx - cfg->pwroff;
|
|
if (req->elm_stat[3] & SESCTL_RQSTON)
|
|
buf[2] = 0x01;
|
|
else
|
|
buf[2] = 0x00;
|
|
buf[3] = 0;
|
|
xfer_len = 16;
|
|
default:
|
|
return (EINVAL);
|
|
}
|
|
break;
|
|
case ELMTYP_FAN:
|
|
if ((req->elm_stat[3] & 0x7) != 0)
|
|
cfg->current_request_stages = 2;
|
|
switch (cfg->current_request_stage) {
|
|
case 0:
|
|
if (req->elm_stat[3] & SESCTL_RQSTFAIL)
|
|
cfg->flag1 |= SAFT_FLG1_ENCFANFAIL;
|
|
else
|
|
cfg->flag1 &= ~SAFT_FLG1_ENCFANFAIL;
|
|
buf[0] = SAFTE_WT_GLOBAL;
|
|
buf[1] = cfg->flag1;
|
|
buf[2] = cfg->flag2;
|
|
buf[3] = 0;
|
|
xfer_len = 16;
|
|
break;
|
|
case 1:
|
|
buf[0] = SAFTE_WT_FANSPD;
|
|
buf[1] = idx;
|
|
if (req->elm_stat[3] & SESCTL_RQSTON) {
|
|
if ((req->elm_stat[3] & 0x7) == 7)
|
|
buf[2] = 4;
|
|
else if ((req->elm_stat[3] & 0x7) >= 5)
|
|
buf[2] = 3;
|
|
else if ((req->elm_stat[3] & 0x7) >= 3)
|
|
buf[2] = 2;
|
|
else
|
|
buf[2] = 1;
|
|
} else
|
|
buf[2] = 0;
|
|
buf[3] = 0;
|
|
xfer_len = 16;
|
|
ep->encstat[3] = req->elm_stat[3] & 0x67;
|
|
default:
|
|
return (EINVAL);
|
|
}
|
|
break;
|
|
case ELMTYP_DOORLOCK:
|
|
if (req->elm_stat[3] & 0x1)
|
|
cfg->flag2 &= ~SAFT_FLG2_LOCKDOOR;
|
|
else
|
|
cfg->flag2 |= SAFT_FLG2_LOCKDOOR;
|
|
buf[0] = SAFTE_WT_GLOBAL;
|
|
buf[1] = cfg->flag1;
|
|
buf[2] = cfg->flag2;
|
|
buf[3] = 0;
|
|
xfer_len = 16;
|
|
break;
|
|
case ELMTYP_ALARM:
|
|
if ((req->elm_stat[0] & SESCTL_DISABLE) ||
|
|
(req->elm_stat[3] & 0x40)) {
|
|
cfg->flag2 &= ~SAFT_FLG1_ALARM;
|
|
} else if ((req->elm_stat[3] & 0x0f) != 0) {
|
|
cfg->flag2 |= SAFT_FLG1_ALARM;
|
|
} else {
|
|
cfg->flag2 &= ~SAFT_FLG1_ALARM;
|
|
}
|
|
buf[0] = SAFTE_WT_GLOBAL;
|
|
buf[1] = cfg->flag1;
|
|
buf[2] = cfg->flag2;
|
|
buf[3] = 0;
|
|
xfer_len = 16;
|
|
ep->encstat[3] = req->elm_stat[3];
|
|
break;
|
|
default:
|
|
return (EINVAL);
|
|
}
|
|
}
|
|
|
|
if (enc->enc_type == ENC_SEMB_SAFT) {
|
|
semb_write_buffer(&ccb->ataio, /*retries*/5,
|
|
NULL, MSG_SIMPLE_Q_TAG,
|
|
buf, xfer_len, state->timeout);
|
|
} else {
|
|
scsi_write_buffer(&ccb->csio, /*retries*/5,
|
|
NULL, MSG_SIMPLE_Q_TAG, 1,
|
|
0, 0, buf, xfer_len,
|
|
SSD_FULL_SIZE, state->timeout);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
safte_process_control_request(enc_softc_t *enc, struct enc_fsm_state *state,
|
|
union ccb *ccb, uint8_t **bufp, int error, int xfer_len)
|
|
{
|
|
struct scfg *cfg;
|
|
safte_control_request_t *req;
|
|
int idx, type;
|
|
|
|
cfg = enc->enc_private;
|
|
if (cfg == NULL)
|
|
return (ENXIO);
|
|
|
|
req = cfg->current_request;
|
|
if (req->result == 0)
|
|
req->result = error;
|
|
if (++cfg->current_request_stage >= cfg->current_request_stages) {
|
|
idx = req->elm_idx;
|
|
if (idx == SES_SETSTATUS_ENC_IDX)
|
|
type = -1;
|
|
else
|
|
type = enc->enc_cache.elm_map[idx].enctype;
|
|
if (type == ELMTYP_DEVICE || type == ELMTYP_ARRAY_DEV)
|
|
enc_update_request(enc, SAFTE_UPDATE_READSLOTSTATUS);
|
|
else
|
|
enc_update_request(enc, SAFTE_UPDATE_READENCSTATUS);
|
|
cfg->current_request = NULL;
|
|
wakeup(req);
|
|
} else {
|
|
enc_update_request(enc, SAFTE_PROCESS_CONTROL_REQS);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
safte_softc_invalidate(enc_softc_t *enc)
|
|
{
|
|
struct scfg *cfg;
|
|
|
|
cfg = enc->enc_private;
|
|
safte_terminate_control_requests(&cfg->requests, ENXIO);
|
|
}
|
|
|
|
static void
|
|
safte_softc_cleanup(enc_softc_t *enc)
|
|
{
|
|
|
|
ENC_FREE_AND_NULL(enc->enc_cache.elm_map);
|
|
ENC_FREE_AND_NULL(enc->enc_private);
|
|
enc->enc_cache.nelms = 0;
|
|
}
|
|
|
|
static int
|
|
safte_init_enc(enc_softc_t *enc)
|
|
{
|
|
struct scfg *cfg;
|
|
int err;
|
|
static char cdb0[6] = { SEND_DIAGNOSTIC };
|
|
|
|
cfg = enc->enc_private;
|
|
if (cfg == NULL)
|
|
return (ENXIO);
|
|
|
|
err = enc_runcmd(enc, cdb0, 6, NULL, 0);
|
|
if (err) {
|
|
return (err);
|
|
}
|
|
DELAY(5000);
|
|
cfg->flag1 = 0;
|
|
cfg->flag2 = 0;
|
|
err = safte_set_enc_status(enc, 0, 1);
|
|
return (err);
|
|
}
|
|
|
|
static int
|
|
safte_get_enc_status(enc_softc_t *enc, int slpflg)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
safte_set_enc_status(enc_softc_t *enc, uint8_t encstat, int slpflag)
|
|
{
|
|
struct scfg *cfg;
|
|
safte_control_request_t req;
|
|
|
|
cfg = enc->enc_private;
|
|
if (cfg == NULL)
|
|
return (ENXIO);
|
|
|
|
req.elm_idx = SES_SETSTATUS_ENC_IDX;
|
|
req.elm_stat[0] = encstat & 0xf;
|
|
req.result = 0;
|
|
|
|
TAILQ_INSERT_TAIL(&cfg->requests, &req, links);
|
|
enc_update_request(enc, SAFTE_PROCESS_CONTROL_REQS);
|
|
cam_periph_sleep(enc->periph, &req, PUSER, "encstat", 0);
|
|
|
|
return (req.result);
|
|
}
|
|
|
|
static int
|
|
safte_get_elm_status(enc_softc_t *enc, encioc_elm_status_t *elms, int slpflg)
|
|
{
|
|
int i = (int)elms->elm_idx;
|
|
|
|
elms->cstat[0] = enc->enc_cache.elm_map[i].encstat[0];
|
|
elms->cstat[1] = enc->enc_cache.elm_map[i].encstat[1];
|
|
elms->cstat[2] = enc->enc_cache.elm_map[i].encstat[2];
|
|
elms->cstat[3] = enc->enc_cache.elm_map[i].encstat[3];
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
safte_set_elm_status(enc_softc_t *enc, encioc_elm_status_t *elms, int slpflag)
|
|
{
|
|
struct scfg *cfg;
|
|
safte_control_request_t req;
|
|
|
|
cfg = enc->enc_private;
|
|
if (cfg == NULL)
|
|
return (ENXIO);
|
|
|
|
/* If this is clear, we don't do diddly. */
|
|
if ((elms->cstat[0] & SESCTL_CSEL) == 0)
|
|
return (0);
|
|
|
|
req.elm_idx = elms->elm_idx;
|
|
memcpy(&req.elm_stat, elms->cstat, sizeof(req.elm_stat));
|
|
req.result = 0;
|
|
|
|
TAILQ_INSERT_TAIL(&cfg->requests, &req, links);
|
|
enc_update_request(enc, SAFTE_PROCESS_CONTROL_REQS);
|
|
cam_periph_sleep(enc->periph, &req, PUSER, "encstat", 0);
|
|
|
|
return (req.result);
|
|
}
|
|
|
|
static void
|
|
safte_poll_status(enc_softc_t *enc)
|
|
{
|
|
|
|
enc_update_request(enc, SAFTE_UPDATE_READENCSTATUS);
|
|
enc_update_request(enc, SAFTE_UPDATE_READSLOTSTATUS);
|
|
}
|
|
|
|
static struct enc_vec safte_enc_vec =
|
|
{
|
|
.softc_invalidate = safte_softc_invalidate,
|
|
.softc_cleanup = safte_softc_cleanup,
|
|
.init_enc = safte_init_enc,
|
|
.get_enc_status = safte_get_enc_status,
|
|
.set_enc_status = safte_set_enc_status,
|
|
.get_elm_status = safte_get_elm_status,
|
|
.set_elm_status = safte_set_elm_status,
|
|
.poll_status = safte_poll_status
|
|
};
|
|
|
|
int
|
|
safte_softc_init(enc_softc_t *enc)
|
|
{
|
|
struct scfg *cfg;
|
|
|
|
enc->enc_vec = safte_enc_vec;
|
|
enc->enc_fsm_states = enc_fsm_states;
|
|
|
|
if (enc->enc_private == NULL) {
|
|
enc->enc_private = ENC_MALLOCZ(SAFT_PRIVATE);
|
|
if (enc->enc_private == NULL)
|
|
return (ENOMEM);
|
|
}
|
|
cfg = enc->enc_private;
|
|
|
|
enc->enc_cache.nelms = 0;
|
|
enc->enc_cache.enc_status = 0;
|
|
|
|
TAILQ_INIT(&cfg->requests);
|
|
return (0);
|
|
}
|
|
|