693f8b3673
Newbus handles multiple equally named device classes without problems, so there is no reason to use slightly cryptic "<foo>_shdci" for them. In contrast, the driver module name must be unique, so "<foo>_shdci" is the right name for it.
468 lines
12 KiB
C
468 lines
12 KiB
C
/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* SDHCI driver glue for NVIDIA Tegra family
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*
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/types.h>
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#include <sys/bus.h>
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#include <sys/gpio.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/mmc/bridge.h>
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#include <dev/mmc/mmcbrvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/sdhci/sdhci.h>
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#include <dev/sdhci/sdhci_fdt_gpio.h>
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#include "sdhci_if.h"
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/* Tegra SDHOST controller vendor register definitions */
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#define SDMMC_VENDOR_CLOCK_CNTRL 0x100
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#define VENDOR_CLOCK_CNTRL_CLK_SHIFT 8
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#define VENDOR_CLOCK_CNTRL_CLK_MASK 0xFF
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#define SDMMC_VENDOR_SYS_SW_CNTRL 0x104
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#define SDMMC_VENDOR_CAP_OVERRIDES 0x10C
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#define SDMMC_VENDOR_BOOT_CNTRL 0x110
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#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT 0x114
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#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT 0x118
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#define SDMMC_VENDOR_DEBOUNCE_COUNT 0x11C
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#define SDMMC_VENDOR_MISC_CNTRL 0x120
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#define VENDOR_MISC_CTRL_ENABLE_SDR104 0x8
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#define VENDOR_MISC_CTRL_ENABLE_SDR50 0x10
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#define VENDOR_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
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#define VENDOR_MISC_CTRL_ENABLE_DDR50 0x200
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#define SDMMC_MAX_CURRENT_OVERRIDE 0x124
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#define SDMMC_MAX_CURRENT_OVERRIDE_HI 0x128
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#define SDMMC_VENDOR_CLK_GATE_HYSTERESIS_COUNT 0x1D0
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#define SDMMC_VENDOR_PHWRESET_VAL0 0x1D4
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#define SDMMC_VENDOR_PHWRESET_VAL1 0x1D8
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#define SDMMC_VENDOR_PHWRESET_VAL2 0x1DC
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#define SDMMC_SDMEMCOMPPADCTRL_0 0x1E0
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#define SDMMC_AUTO_CAL_CONFIG 0x1E4
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#define SDMMC_AUTO_CAL_INTERVAL 0x1E8
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#define SDMMC_AUTO_CAL_STATUS 0x1EC
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#define SDMMC_SDMMC_MCCIF_FIFOCTRL 0x1F4
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#define SDMMC_TIMEOUT_WCOAL_SDMMC 0x1F8
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/* Compatible devices. */
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static struct ofw_compat_data compat_data[] = {
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{"nvidia,tegra124-sdhci", 1},
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{NULL, 0},
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};
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struct tegra_sdhci_softc {
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device_t dev;
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struct resource * mem_res;
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struct resource * irq_res;
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void * intr_cookie;
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u_int quirks; /* Chip specific quirks */
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u_int caps; /* If we override SDHCI_CAPABILITIES */
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uint32_t max_clk; /* Max possible freq */
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clk_t clk;
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hwreset_t reset;
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gpio_pin_t gpio_power;
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struct sdhci_fdt_gpio *gpio;
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int force_card_present;
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struct sdhci_slot slot;
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};
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static inline uint32_t
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RD4(struct tegra_sdhci_softc *sc, bus_size_t off)
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{
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return (bus_read_4(sc->mem_res, off));
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}
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static uint8_t
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tegra_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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{
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struct tegra_sdhci_softc *sc;
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sc = device_get_softc(dev);
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return (bus_read_1(sc->mem_res, off));
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}
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static uint16_t
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tegra_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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{
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struct tegra_sdhci_softc *sc;
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sc = device_get_softc(dev);
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return (bus_read_2(sc->mem_res, off));
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}
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static uint32_t
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tegra_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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{
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struct tegra_sdhci_softc *sc;
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uint32_t val32;
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sc = device_get_softc(dev);
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val32 = bus_read_4(sc->mem_res, off);
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/* Force the card-present state if necessary. */
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if (off == SDHCI_PRESENT_STATE && sc->force_card_present)
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val32 |= SDHCI_CARD_PRESENT;
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return (val32);
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}
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static void
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tegra_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint32_t *data, bus_size_t count)
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{
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struct tegra_sdhci_softc *sc;
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sc = device_get_softc(dev);
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bus_read_multi_4(sc->mem_res, off, data, count);
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}
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static void
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tegra_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint8_t val)
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{
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struct tegra_sdhci_softc *sc;
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sc = device_get_softc(dev);
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bus_write_1(sc->mem_res, off, val);
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}
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static void
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tegra_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint16_t val)
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{
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struct tegra_sdhci_softc *sc;
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sc = device_get_softc(dev);
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bus_write_2(sc->mem_res, off, val);
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}
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static void
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tegra_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint32_t val)
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{
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struct tegra_sdhci_softc *sc;
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sc = device_get_softc(dev);
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bus_write_4(sc->mem_res, off, val);
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}
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static void
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tegra_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint32_t *data, bus_size_t count)
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{
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struct tegra_sdhci_softc *sc;
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sc = device_get_softc(dev);
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bus_write_multi_4(sc->mem_res, off, data, count);
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}
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static void
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tegra_sdhci_intr(void *arg)
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{
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struct tegra_sdhci_softc *sc = arg;
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sdhci_generic_intr(&sc->slot);
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RD4(sc, SDHCI_INT_STATUS);
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}
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static int
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tegra_sdhci_get_ro(device_t brdev, device_t reqdev)
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{
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struct tegra_sdhci_softc *sc = device_get_softc(brdev);
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return (sdhci_fdt_gpio_get_readonly(sc->gpio));
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}
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static bool
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tegra_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
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{
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struct tegra_sdhci_softc *sc = device_get_softc(dev);
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return (sdhci_fdt_gpio_get_present(sc->gpio));
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}
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static int
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tegra_sdhci_probe(device_t dev)
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{
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struct tegra_sdhci_softc *sc;
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phandle_t node;
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pcell_t cid;
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const struct ofw_compat_data *cd;
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sc = device_get_softc(dev);
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_is_compatible(dev, "nvidia,tegra124-sdhci")) {
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device_set_desc(dev, "Tegra SDHCI controller");
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} else
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return (ENXIO);
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cd = ofw_bus_search_compatible(dev, compat_data);
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if (cd->ocd_data == 0)
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return (ENXIO);
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node = ofw_bus_get_node(dev);
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/* Allow dts to patch quirks, slots, and max-frequency. */
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if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0)
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sc->quirks = cid;
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if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0)
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sc->max_clk = cid;
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return (BUS_PROBE_DEFAULT);
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}
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static int
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tegra_sdhci_attach(device_t dev)
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{
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struct tegra_sdhci_softc *sc;
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int rid, rv;
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uint64_t freq;
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phandle_t node, prop;
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sc = device_get_softc(dev);
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sc->dev = dev;
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node = ofw_bus_get_node(dev);
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->mem_res) {
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device_printf(dev, "cannot allocate memory window\n");
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rv = ENXIO;
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goto fail;
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}
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rid = 0;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (!sc->irq_res) {
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device_printf(dev, "cannot allocate interrupt\n");
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rv = ENXIO;
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goto fail;
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}
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if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
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NULL, tegra_sdhci_intr, sc, &sc->intr_cookie)) {
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device_printf(dev, "cannot setup interrupt handler\n");
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rv = ENXIO;
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goto fail;
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}
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rv = hwreset_get_by_ofw_name(sc->dev, 0, "sdhci", &sc->reset);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'sdhci' reset\n");
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goto fail;
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}
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rv = hwreset_deassert(sc->reset);
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if (rv != 0) {
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device_printf(dev, "Cannot unreset 'sdhci' reset\n");
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goto fail;
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}
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gpio_pin_get_by_ofw_property(sc->dev, node, "power-gpios", &sc->gpio_power);
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rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
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if (rv != 0) {
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device_printf(dev, "Cannot get clock\n");
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goto fail;
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}
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rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
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if (rv != 0) {
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device_printf(dev, "Cannot get clock\n");
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goto fail;
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}
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rv = clk_enable(sc->clk);
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if (rv != 0) {
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device_printf(dev, "Cannot enable clock\n");
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goto fail;
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}
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rv = clk_set_freq(sc->clk, 48000000, CLK_SET_ROUND_DOWN);
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if (rv != 0) {
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device_printf(dev, "Cannot set clock\n");
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}
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rv = clk_get_freq(sc->clk, &freq);
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if (rv != 0) {
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device_printf(dev, "Cannot get clock frequency\n");
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goto fail;
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}
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if (bootverbose)
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device_printf(dev, " Base MMC clock: %lld\n", freq);
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/* Fill slot information. */
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sc->max_clk = (int)freq;
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sc->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_MISSING_CAPS;
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/* Limit real slot capabilities. */
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sc->caps = RD4(sc, SDHCI_CAPABILITIES);
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if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) {
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sc->caps &= ~(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
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switch (prop) {
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case 8:
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sc->caps |= MMC_CAP_8_BIT_DATA;
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/* FALLTHROUGH */
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case 4:
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sc->caps |= MMC_CAP_4_BIT_DATA;
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break;
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case 1:
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break;
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default:
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device_printf(dev, "Bad bus-width value %u\n", prop);
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break;
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}
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}
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if (OF_hasprop(node, "non-removable"))
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sc->force_card_present = 1;
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/*
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* Clear clock field, so SDHCI driver uses supplied frequency.
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* in sc->slot.max_clk
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*/
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sc->caps &= ~SDHCI_CLOCK_V3_BASE_MASK;
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sc->slot.quirks = sc->quirks;
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sc->slot.max_clk = sc->max_clk;
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sc->slot.caps = sc->caps;
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rv = sdhci_init_slot(dev, &sc->slot, 0);
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if (rv != 0) {
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goto fail;
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}
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sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot);
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bus_generic_probe(dev);
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bus_generic_attach(dev);
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sdhci_start_slot(&sc->slot);
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return (0);
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fail:
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if (sc->gpio != NULL)
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sdhci_fdt_gpio_teardown(sc->gpio);
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if (sc->intr_cookie != NULL)
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bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
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if (sc->gpio_power != NULL)
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gpio_pin_release(sc->gpio_power);
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if (sc->clk != NULL)
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clk_release(sc->clk);
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if (sc->reset != NULL)
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hwreset_release(sc->reset);
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if (sc->irq_res != NULL)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
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if (sc->mem_res != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
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return (rv);
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}
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static int
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tegra_sdhci_detach(device_t dev)
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{
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struct tegra_sdhci_softc *sc = device_get_softc(dev);
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struct sdhci_slot *slot = &sc->slot;
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bus_generic_detach(dev);
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sdhci_fdt_gpio_teardown(sc->gpio);
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clk_release(sc->clk);
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bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
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bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
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sc->irq_res);
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sdhci_cleanup_slot(slot);
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bus_release_resource(dev, SYS_RES_MEMORY,
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rman_get_rid(sc->mem_res),
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sc->mem_res);
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return (0);
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}
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static device_method_t tegra_sdhci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, tegra_sdhci_probe),
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DEVMETHOD(device_attach, tegra_sdhci_attach),
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DEVMETHOD(device_detach, tegra_sdhci_detach),
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/* Bus interface */
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DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
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DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
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/* MMC bridge interface */
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DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
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DEVMETHOD(mmcbr_request, sdhci_generic_request),
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DEVMETHOD(mmcbr_get_ro, tegra_sdhci_get_ro),
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DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
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DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
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/* SDHCI registers accessors */
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DEVMETHOD(sdhci_read_1, tegra_sdhci_read_1),
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DEVMETHOD(sdhci_read_2, tegra_sdhci_read_2),
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DEVMETHOD(sdhci_read_4, tegra_sdhci_read_4),
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DEVMETHOD(sdhci_read_multi_4, tegra_sdhci_read_multi_4),
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DEVMETHOD(sdhci_write_1, tegra_sdhci_write_1),
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DEVMETHOD(sdhci_write_2, tegra_sdhci_write_2),
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DEVMETHOD(sdhci_write_4, tegra_sdhci_write_4),
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DEVMETHOD(sdhci_write_multi_4, tegra_sdhci_write_multi_4),
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DEVMETHOD(sdhci_get_card_present, tegra_sdhci_get_card_present),
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DEVMETHOD_END
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};
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static devclass_t tegra_sdhci_devclass;
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static DEFINE_CLASS_0(sdhci, tegra_sdhci_driver, tegra_sdhci_methods,
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sizeof(struct tegra_sdhci_softc));
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DRIVER_MODULE(sdhci_tegra, simplebus, tegra_sdhci_driver, tegra_sdhci_devclass,
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NULL, NULL);
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MODULE_DEPEND(sdhci_tegra, sdhci, 1, 1, 1);
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MMC_DECLARE_BRIDGE(sdhci);
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