263 lines
7.1 KiB
C
263 lines
7.1 KiB
C
/*
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* FreeBSD, PCI product support functions
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*
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* Copyright (c) 1995-2001 Justin T. Gibbs
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU Public License ("GPL").
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/ahc_pci.c#9 $
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*
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* $FreeBSD$
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*/
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#include <dev/aic7xxx/aic7xxx_osm.h>
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#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */
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#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
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static int ahc_pci_probe(device_t dev);
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static int ahc_pci_attach(device_t dev);
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static device_method_t ahc_pci_device_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ahc_pci_probe),
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DEVMETHOD(device_attach, ahc_pci_attach),
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DEVMETHOD(device_detach, ahc_detach),
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{ 0, 0 }
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};
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static driver_t ahc_pci_driver = {
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"ahc",
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ahc_pci_device_methods,
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sizeof(struct ahc_softc)
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};
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DRIVER_MODULE(ahc_pci, pci, ahc_pci_driver, ahc_devclass, 0, 0);
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DRIVER_MODULE(ahc_pci, cardbus, ahc_pci_driver, ahc_devclass, 0, 0);
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MODULE_DEPEND(ahc_pci, ahc, 1, 1, 1);
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MODULE_VERSION(ahc_pci, 1);
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static int
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ahc_pci_probe(device_t dev)
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{
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struct ahc_pci_identity *entry;
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entry = ahc_find_pci_device(dev);
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if (entry != NULL) {
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device_set_desc(dev, entry->name);
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return (0);
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}
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return (ENXIO);
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}
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static int
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ahc_pci_attach(device_t dev)
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{
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struct ahc_pci_identity *entry;
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struct ahc_softc *ahc;
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char *name;
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int error;
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entry = ahc_find_pci_device(dev);
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if (entry == NULL)
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return (ENXIO);
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/*
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* Allocate a softc for this card and
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* set it up for attachment by our
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* common detect routine.
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*/
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name = malloc(strlen(device_get_nameunit(dev)) + 1, M_DEVBUF, M_NOWAIT);
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if (name == NULL)
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return (ENOMEM);
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strcpy(name, device_get_nameunit(dev));
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ahc = ahc_alloc(dev, name);
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if (ahc == NULL)
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return (ENOMEM);
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ahc_set_unit(ahc, device_get_unit(dev));
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/*
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* Should we bother disabling 39Bit addressing
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* based on installed memory?
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*/
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if (sizeof(bus_addr_t) > 4)
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ahc->flags |= AHC_39BIT_ADDRESSING;
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/* Allocate a dmatag for our SCB DMA maps */
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/* XXX Should be a child of the PCI bus dma tag */
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error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
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/*boundary*/0,
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(ahc->flags & AHC_39BIT_ADDRESSING)
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? 0x7FFFFFFFFF
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: BUS_SPACE_MAXADDR_32BIT,
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/*highaddr*/BUS_SPACE_MAXADDR,
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/*filter*/NULL, /*filterarg*/NULL,
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/*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG,
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/*maxsegsz*/AHC_MAXTRANSFER_SIZE,
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/*flags*/BUS_DMA_ALLOCNOW,
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&ahc->parent_dmat);
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if (error != 0) {
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printf("ahc_pci_attach: Could not allocate DMA tag "
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"- error %d\n", error);
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ahc_free(ahc);
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return (ENOMEM);
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}
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ahc->dev_softc = dev;
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error = ahc_pci_config(ahc, entry);
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if (error != 0) {
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ahc_free(ahc);
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return (error);
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}
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ahc_attach(ahc);
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return (0);
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}
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int
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ahc_pci_map_registers(struct ahc_softc *ahc)
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{
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struct resource *regs;
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u_int command;
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int regs_type;
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int regs_id;
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command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
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regs = NULL;
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regs_type = 0;
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regs_id = 0;
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#ifdef AHC_ALLOW_MEMIO
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if ((command & PCIM_CMD_MEMEN) != 0) {
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regs_type = SYS_RES_MEMORY;
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regs_id = AHC_PCI_MEMADDR;
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regs = bus_alloc_resource(ahc->dev_softc, regs_type,
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®s_id, 0, ~0, 1, RF_ACTIVE);
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if (regs != NULL) {
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ahc->tag = rman_get_bustag(regs);
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ahc->bsh = rman_get_bushandle(regs);
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/*
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* Do a quick test to see if memory mapped
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* I/O is functioning correctly.
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*/
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if (ahc_inb(ahc, HCNTRL) == 0xFF) {
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device_printf(ahc->dev_softc,
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"PCI Device %d:%d:%d failed memory "
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"mapped test. Using PIO.\n",
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ahc_get_pci_bus(ahc->dev_softc),
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ahc_get_pci_slot(ahc->dev_softc),
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ahc_get_pci_function(ahc->dev_softc));
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bus_release_resource(ahc->dev_softc, regs_type,
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regs_id, regs);
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regs = NULL;
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} else {
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command &= ~PCIM_CMD_PORTEN;
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ahc_pci_write_config(ahc->dev_softc,
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PCIR_COMMAND,
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command, /*bytes*/1);
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}
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}
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}
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#endif
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if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
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regs_type = SYS_RES_IOPORT;
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regs_id = AHC_PCI_IOADDR;
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regs = bus_alloc_resource(ahc->dev_softc, regs_type,
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®s_id, 0, ~0, 1, RF_ACTIVE);
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if (regs != NULL) {
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ahc->tag = rman_get_bustag(regs);
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ahc->bsh = rman_get_bushandle(regs);
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command &= ~PCIM_CMD_MEMEN;
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ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
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command, /*bytes*/1);
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}
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}
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if (regs == NULL) {
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device_printf(ahc->dev_softc,
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"can't allocate register resources\n");
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return (ENOMEM);
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}
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ahc->platform_data->regs_res_type = regs_type;
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ahc->platform_data->regs_res_id = regs_id;
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ahc->platform_data->regs = regs;
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return (0);
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}
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int
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ahc_pci_map_int(struct ahc_softc *ahc)
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{
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int zero;
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zero = 0;
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ahc->platform_data->irq =
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bus_alloc_resource(ahc->dev_softc, SYS_RES_IRQ, &zero,
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0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
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if (ahc->platform_data->irq == NULL) {
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device_printf(ahc->dev_softc,
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"bus_alloc_resource() failed to allocate IRQ\n");
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return (ENOMEM);
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}
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ahc->platform_data->irq_res_type = SYS_RES_IRQ;
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return (ahc_map_int(ahc));
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}
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void
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ahc_power_state_change(struct ahc_softc *ahc, ahc_power_state new_state)
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{
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uint32_t cap;
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u_int cap_offset;
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/*
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* Traverse the capability list looking for
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* the power management capability.
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*/
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cap = 0;
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cap_offset = ahc_pci_read_config(ahc->dev_softc,
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PCIR_CAP_PTR, /*bytes*/1);
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while (cap_offset != 0) {
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cap = ahc_pci_read_config(ahc->dev_softc,
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cap_offset, /*bytes*/4);
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if ((cap & 0xFF) == 1
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&& ((cap >> 16) & 0x3) > 0) {
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uint32_t pm_control;
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pm_control = ahc_pci_read_config(ahc->dev_softc,
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cap_offset + 4,
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/*bytes*/2);
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pm_control &= ~0x3;
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pm_control |= new_state;
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ahc_pci_write_config(ahc->dev_softc,
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cap_offset + 4,
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pm_control, /*bytes*/2);
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break;
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}
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cap_offset = (cap >> 8) & 0xFF;
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}
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}
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