Olivier Houchard 4cd3385ee3 If our buffer is not aligned on the cache line size, write back/invalidate ...

the first and last cache line in PREREAD, and just invalidate the cache
lines in POSTREAD, instead of write-back/invalidating in POSTREAD, which
could lead to stale data overriding what has been transfered by DMA.

2006-05-31 15:50:33 +00:00

..

arm

If our buffer is not aligned on the cache line size, write back/invalidate

2006-05-31 15:50:33 +00:00

at91

We have an implementation of generic_bs_rr_1, so use it, as some drivers use

2006-05-19 11:27:02 +00:00

compile

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conf

Comment out SYSCTL_OMIT_DESCR until it's committed.

2006-05-19 00:11:21 +00:00

include

Ooops arm10 is armv5, not armv4.

2006-05-31 13:06:08 +00:00

sa11x0

The Assabet has 32MB of RAM, not 16.

2006-05-30 15:47:55 +00:00

xscale

Remove any reference to enable_mmu(), it's been gone for a long time.

2006-05-26 01:41:47 +00:00