4d7abca057
uart(4) allocates send and receiver buffers in attach() before it calls the low-level driver's attach routine. Many low-level drivers set the fifo sizes in their attach routine, which is too late. Other drivers set them in the probe() routine, so that they're available when uart(4) allocates buffers. This fixes the ones that were setting the values too late by moving the code to probe().
624 lines
14 KiB
C
624 lines
14 KiB
C
/*-
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* Copyright (c) 2003 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <machine/bus.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include <dev/ic/z8530.h>
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#include "uart_if.h"
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#define DEFAULT_RCLK 307200
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/* Hack! */
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#ifdef __powerpc__
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#define UART_PCLK 0
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#else
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#define UART_PCLK MCB2_PCLK
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#endif
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/* Multiplexed I/O. */
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static __inline void
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uart_setmreg(struct uart_bas *bas, int reg, int val)
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{
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uart_setreg(bas, REG_CTRL, reg);
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uart_barrier(bas);
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uart_setreg(bas, REG_CTRL, val);
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}
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static __inline uint8_t
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uart_getmreg(struct uart_bas *bas, int reg)
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{
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uart_setreg(bas, REG_CTRL, reg);
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uart_barrier(bas);
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return (uart_getreg(bas, REG_CTRL));
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}
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static int
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z8530_divisor(int rclk, int baudrate)
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{
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int act_baud, divisor, error;
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if (baudrate == 0)
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return (-1);
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divisor = (rclk + baudrate) / (baudrate << 1) - 2;
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if (divisor < 0 || divisor >= 65536)
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return (-1);
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act_baud = rclk / 2 / (divisor + 2);
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/* 10 times error in percent: */
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error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
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/* 3.0% maximum error tolerance: */
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if (error < -30 || error > 30)
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return (-1);
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return (divisor);
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}
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static int
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z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity, uint8_t *tpcp)
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{
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int divisor;
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uint8_t mpm, rpc, tpc;
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rpc = RPC_RXE;
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mpm = MPM_CM16;
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tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS));
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if (databits >= 8) {
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rpc |= RPC_RB8;
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tpc |= TPC_TB8;
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} else if (databits == 7) {
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rpc |= RPC_RB7;
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tpc |= TPC_TB7;
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} else if (databits == 6) {
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rpc |= RPC_RB6;
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tpc |= TPC_TB6;
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} else {
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rpc |= RPC_RB5;
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tpc |= TPC_TB5;
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}
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mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1;
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switch (parity) {
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case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break;
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case UART_PARITY_NONE: break;
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case UART_PARITY_ODD: mpm |= MPM_PE; break;
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default: return (EINVAL);
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}
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if (baudrate > 0) {
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divisor = z8530_divisor(bas->rclk, baudrate);
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if (divisor == -1)
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return (EINVAL);
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} else
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divisor = -1;
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uart_setmreg(bas, WR_MCB2, UART_PCLK);
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uart_barrier(bas);
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if (divisor >= 0) {
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uart_setmreg(bas, WR_TCL, divisor & 0xff);
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uart_barrier(bas);
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uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff);
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uart_barrier(bas);
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}
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uart_setmreg(bas, WR_RPC, rpc);
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uart_barrier(bas);
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uart_setmreg(bas, WR_MPM, mpm);
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uart_barrier(bas);
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uart_setmreg(bas, WR_TPC, tpc);
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uart_barrier(bas);
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uart_setmreg(bas, WR_MCB2, UART_PCLK | MCB2_BRGE);
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uart_barrier(bas);
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*tpcp = tpc;
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return (0);
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}
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static int
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z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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uint8_t tpc;
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if (bas->rclk == 0)
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bas->rclk = DEFAULT_RCLK;
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/* Assume we don't need to perform a full hardware reset. */
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switch (bas->chan) {
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case 1:
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uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRA);
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break;
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case 2:
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uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRB);
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break;
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}
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uart_barrier(bas);
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/* Set clock sources. */
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uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG);
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uart_setmreg(bas, WR_MCB2, UART_PCLK);
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uart_barrier(bas);
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/* Set data encoding. */
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uart_setmreg(bas, WR_MCB1, MCB1_NRZ);
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uart_barrier(bas);
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tpc = TPC_DTR | TPC_RTS;
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z8530_param(bas, baudrate, databits, stopbits, parity, &tpc);
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return (int)tpc;
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}
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/*
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* Low-level UART interface.
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*/
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static int z8530_probe(struct uart_bas *bas);
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static void z8530_init(struct uart_bas *bas, int, int, int, int);
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static void z8530_term(struct uart_bas *bas);
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static void z8530_putc(struct uart_bas *bas, int);
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static int z8530_rxready(struct uart_bas *bas);
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static int z8530_getc(struct uart_bas *bas, struct mtx *);
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static struct uart_ops uart_z8530_ops = {
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.probe = z8530_probe,
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.init = z8530_init,
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.term = z8530_term,
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.putc = z8530_putc,
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.rxready = z8530_rxready,
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.getc = z8530_getc,
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};
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static int
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z8530_probe(struct uart_bas *bas)
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{
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return (0);
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}
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static void
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z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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z8530_setup(bas, baudrate, databits, stopbits, parity);
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}
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static void
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z8530_term(struct uart_bas *bas)
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{
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}
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static void
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z8530_putc(struct uart_bas *bas, int c)
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{
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while (!(uart_getreg(bas, REG_CTRL) & BES_TXE))
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;
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uart_setreg(bas, REG_DATA, c);
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uart_barrier(bas);
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}
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static int
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z8530_rxready(struct uart_bas *bas)
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{
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return ((uart_getreg(bas, REG_CTRL) & BES_RXA) != 0 ? 1 : 0);
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}
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static int
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z8530_getc(struct uart_bas *bas, struct mtx *hwmtx)
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{
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int c;
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uart_lock(hwmtx);
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while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) {
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uart_unlock(hwmtx);
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DELAY(10);
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uart_lock(hwmtx);
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}
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c = uart_getreg(bas, REG_DATA);
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uart_unlock(hwmtx);
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return (c);
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}
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/*
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* High-level UART interface.
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*/
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struct z8530_softc {
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struct uart_softc base;
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uint8_t tpc;
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uint8_t txidle;
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};
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static int z8530_bus_attach(struct uart_softc *);
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static int z8530_bus_detach(struct uart_softc *);
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static int z8530_bus_flush(struct uart_softc *, int);
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static int z8530_bus_getsig(struct uart_softc *);
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static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int z8530_bus_ipend(struct uart_softc *);
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static int z8530_bus_param(struct uart_softc *, int, int, int, int);
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static int z8530_bus_probe(struct uart_softc *);
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static int z8530_bus_receive(struct uart_softc *);
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static int z8530_bus_setsig(struct uart_softc *, int);
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static int z8530_bus_transmit(struct uart_softc *);
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static kobj_method_t z8530_methods[] = {
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KOBJMETHOD(uart_attach, z8530_bus_attach),
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KOBJMETHOD(uart_detach, z8530_bus_detach),
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KOBJMETHOD(uart_flush, z8530_bus_flush),
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KOBJMETHOD(uart_getsig, z8530_bus_getsig),
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KOBJMETHOD(uart_ioctl, z8530_bus_ioctl),
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KOBJMETHOD(uart_ipend, z8530_bus_ipend),
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KOBJMETHOD(uart_param, z8530_bus_param),
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KOBJMETHOD(uart_probe, z8530_bus_probe),
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KOBJMETHOD(uart_receive, z8530_bus_receive),
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KOBJMETHOD(uart_setsig, z8530_bus_setsig),
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KOBJMETHOD(uart_transmit, z8530_bus_transmit),
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{ 0, 0 }
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};
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struct uart_class uart_z8530_class = {
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"z8530",
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z8530_methods,
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sizeof(struct z8530_softc),
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.uc_ops = &uart_z8530_ops,
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.uc_range = 2,
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.uc_rclk = DEFAULT_RCLK
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};
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#define SIGCHG(c, i, s, d) \
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if (c) { \
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i |= (i & s) ? s : s | d; \
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} else { \
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i = (i & s) ? (i & ~s) | d : i; \
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}
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static int
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z8530_bus_attach(struct uart_softc *sc)
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{
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struct z8530_softc *z8530 = (struct z8530_softc*)sc;
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struct uart_bas *bas;
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struct uart_devinfo *di;
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bas = &sc->sc_bas;
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if (sc->sc_sysdev != NULL) {
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di = sc->sc_sysdev;
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z8530->tpc = TPC_DTR|TPC_RTS;
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z8530_param(bas, di->baudrate, di->databits, di->stopbits,
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di->parity, &z8530->tpc);
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} else {
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z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
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z8530->tpc &= ~(TPC_DTR|TPC_RTS);
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}
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z8530->txidle = 1; /* Report SER_INT_TXIDLE. */
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(void)z8530_bus_getsig(sc);
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uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD);
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uart_barrier(bas);
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uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA);
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uart_barrier(bas);
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uart_setmreg(bas, WR_IV, 0);
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uart_barrier(bas);
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uart_setmreg(bas, WR_TPC, z8530->tpc);
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uart_barrier(bas);
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uart_setmreg(bas, WR_MIC, MIC_NV | MIC_MIE);
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uart_barrier(bas);
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return (0);
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}
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static int
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z8530_bus_detach(struct uart_softc *sc)
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{
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return (0);
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}
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static int
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z8530_bus_flush(struct uart_softc *sc, int what)
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{
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return (0);
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}
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static int
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z8530_bus_getsig(struct uart_softc *sc)
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{
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uint32_t new, old, sig;
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uint8_t bes;
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do {
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old = sc->sc_hwsig;
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sig = old;
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uart_lock(sc->sc_hwmtx);
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bes = uart_getmreg(&sc->sc_bas, RR_BES);
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uart_unlock(sc->sc_hwmtx);
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SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
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SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
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SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
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new = sig & ~SER_MASK_DELTA;
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} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
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return (sig);
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}
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static int
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z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
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{
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struct z8530_softc *z8530 = (struct z8530_softc*)sc;
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struct uart_bas *bas;
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int baudrate, divisor, error;
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bas = &sc->sc_bas;
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error = 0;
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uart_lock(sc->sc_hwmtx);
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switch (request) {
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case UART_IOCTL_BREAK:
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if (data)
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z8530->tpc |= TPC_BRK;
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else
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z8530->tpc &= ~TPC_BRK;
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uart_setmreg(bas, WR_TPC, z8530->tpc);
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uart_barrier(bas);
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break;
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case UART_IOCTL_BAUD:
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divisor = uart_getmreg(bas, RR_TCH);
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divisor = (divisor << 8) | uart_getmreg(bas, RR_TCL);
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baudrate = bas->rclk / 2 / (divisor + 2);
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*(int*)data = baudrate;
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break;
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default:
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error = EINVAL;
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break;
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}
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uart_unlock(sc->sc_hwmtx);
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return (error);
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}
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static int
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z8530_bus_ipend(struct uart_softc *sc)
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{
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struct z8530_softc *z8530 = (struct z8530_softc*)sc;
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struct uart_bas *bas;
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int ipend;
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uint32_t sig;
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uint8_t bes, ip, iv, src;
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bas = &sc->sc_bas;
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ipend = 0;
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uart_lock(sc->sc_hwmtx);
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switch (bas->chan) {
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case 1:
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ip = uart_getmreg(bas, RR_IP);
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break;
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case 2: /* XXX hack!!! */
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iv = uart_getmreg(bas, RR_IV) & 0x0E;
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switch (iv) {
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case IV_TEB: ip = IP_TIA; break;
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case IV_XSB: ip = IP_SIA; break;
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case IV_RAB: ip = IP_RIA; break;
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default: ip = 0; break;
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}
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break;
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default:
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ip = 0;
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break;
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}
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if (ip & IP_RIA)
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ipend |= SER_INT_RXREADY;
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if (ip & IP_TIA) {
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uart_setreg(bas, REG_CTRL, CR_RSTTXI);
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uart_barrier(bas);
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if (z8530->txidle) {
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ipend |= SER_INT_TXIDLE;
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z8530->txidle = 0; /* Mask SER_INT_TXIDLE. */
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}
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}
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if (ip & IP_SIA) {
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uart_setreg(bas, REG_CTRL, CR_RSTXSI);
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uart_barrier(bas);
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bes = uart_getmreg(bas, RR_BES);
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if (bes & BES_BRK)
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ipend |= SER_INT_BREAK;
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sig = sc->sc_hwsig;
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SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
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SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
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SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
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if (sig & SER_MASK_DELTA)
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ipend |= SER_INT_SIGCHG;
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src = uart_getmreg(bas, RR_SRC);
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if (src & SRC_OVR) {
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uart_setreg(bas, REG_CTRL, CR_RSTERR);
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uart_barrier(bas);
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ipend |= SER_INT_OVERRUN;
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}
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}
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if (ipend) {
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uart_setreg(bas, REG_CTRL, CR_RSTIUS);
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uart_barrier(bas);
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}
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uart_unlock(sc->sc_hwmtx);
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return (ipend);
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}
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static int
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z8530_bus_param(struct uart_softc *sc, int baudrate, int databits,
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int stopbits, int parity)
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{
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struct z8530_softc *z8530 = (struct z8530_softc*)sc;
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|
int error;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity,
|
|
&z8530->tpc);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
z8530_bus_probe(struct uart_softc *sc)
|
|
{
|
|
char buf[80];
|
|
int error;
|
|
char ch;
|
|
|
|
error = z8530_probe(&sc->sc_bas);
|
|
if (error)
|
|
return (error);
|
|
|
|
sc->sc_rxfifosz = 3;
|
|
sc->sc_txfifosz = 1;
|
|
|
|
ch = sc->sc_bas.chan - 1 + 'A';
|
|
|
|
snprintf(buf, sizeof(buf), "z8530, channel %c", ch);
|
|
device_set_desc_copy(sc->sc_dev, buf);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
z8530_bus_receive(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
int xc;
|
|
uint8_t bes, src;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
bes = uart_getmreg(bas, RR_BES);
|
|
while (bes & BES_RXA) {
|
|
if (uart_rx_full(sc)) {
|
|
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
|
|
break;
|
|
}
|
|
xc = uart_getreg(bas, REG_DATA);
|
|
uart_barrier(bas);
|
|
src = uart_getmreg(bas, RR_SRC);
|
|
if (src & SRC_FE)
|
|
xc |= UART_STAT_FRAMERR;
|
|
if (src & SRC_PE)
|
|
xc |= UART_STAT_PARERR;
|
|
if (src & SRC_OVR)
|
|
xc |= UART_STAT_OVERRUN;
|
|
uart_rx_put(sc, xc);
|
|
if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
|
|
uart_setreg(bas, REG_CTRL, CR_RSTERR);
|
|
uart_barrier(bas);
|
|
}
|
|
bes = uart_getmreg(bas, RR_BES);
|
|
}
|
|
/* Discard everything left in the Rx FIFO. */
|
|
while (bes & BES_RXA) {
|
|
(void)uart_getreg(bas, REG_DATA);
|
|
uart_barrier(bas);
|
|
src = uart_getmreg(bas, RR_SRC);
|
|
if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
|
|
uart_setreg(bas, REG_CTRL, CR_RSTERR);
|
|
uart_barrier(bas);
|
|
}
|
|
bes = uart_getmreg(bas, RR_BES);
|
|
}
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
z8530_bus_setsig(struct uart_softc *sc, int sig)
|
|
{
|
|
struct z8530_softc *z8530 = (struct z8530_softc*)sc;
|
|
struct uart_bas *bas;
|
|
uint32_t new, old;
|
|
|
|
bas = &sc->sc_bas;
|
|
do {
|
|
old = sc->sc_hwsig;
|
|
new = old;
|
|
if (sig & SER_DDTR) {
|
|
SIGCHG(sig & SER_DTR, new, SER_DTR,
|
|
SER_DDTR);
|
|
}
|
|
if (sig & SER_DRTS) {
|
|
SIGCHG(sig & SER_RTS, new, SER_RTS,
|
|
SER_DRTS);
|
|
}
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
if (new & SER_DTR)
|
|
z8530->tpc |= TPC_DTR;
|
|
else
|
|
z8530->tpc &= ~TPC_DTR;
|
|
if (new & SER_RTS)
|
|
z8530->tpc |= TPC_RTS;
|
|
else
|
|
z8530->tpc &= ~TPC_RTS;
|
|
uart_setmreg(bas, WR_TPC, z8530->tpc);
|
|
uart_barrier(bas);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
z8530_bus_transmit(struct uart_softc *sc)
|
|
{
|
|
struct z8530_softc *z8530 = (struct z8530_softc*)sc;
|
|
struct uart_bas *bas;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
while (!(uart_getmreg(bas, RR_BES) & BES_TXE))
|
|
;
|
|
uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]);
|
|
uart_barrier(bas);
|
|
sc->sc_txbusy = 1;
|
|
z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|