29332c0dce
This adds support for the IPQ4018/IPQ4019 MDIO bus. This is used to talk to external PHYs and switches. (There's an internal switch in the IPQ4018/IPQ4019 as well, but it's accessible via MMIO/AXI.) Differential Revision: https://reviews.freebsd.org/D34110 Reviewed by: manu
45 lines
2.0 KiB
C
45 lines
2.0 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __QCOM_MDIO_IPQ4018_REG_H__
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#define __QCOM_MDIO_IPQ4018_REG_H__
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#define QCOM_IPQ4018_MDIO_REG_ADDR 0x44
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#define QCOM_IPQ4018_MDIO_REG_WRITE 0x48
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#define QCOM_IPQ4018_MDIO_REG_READ 0x4c
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#define QCOM_IPQ4018_MDIO_REG_CMD 0x50
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#define QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_BUSY (1U << 16)
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#define QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_START (1U << 8)
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#define QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_CODE_READ 0
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#define QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_CODE_WRITE 1
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#define QCOM_IPQ4018_MDIO_SLEEP_COUNT 100
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#define QCOM_IPQ4018_MDIO_SLEEP 10 /* uSec */
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#endif /* __QCOM_MDIO_IPQ4018_REG_H__ */
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