254e4e5b77
When a DMA request using bounce pages completes, a swi is triggered to schedule pending DMA requests using the just-freed bounce pages. For a long time this bus_dma swi has been tied to a "virtual memory" swi (swi_vm). However, all of the swi_vm implementations are the same and consist of checking a flag (busdma_swi_pending) which is always true and if set calling busdma_swi. I suspect this dates back to the pre-SMPng days and that the intention was for swi_vm to serve as a mux. However, in the current scheme there's no need for the mux. Instead, remove swi_vm and vm_ih. Each bus_dma implementation that uses bounce pages is responsible for creating its own swi (busdma_ih) which it now schedules directly. This swi invokes busdma_swi directly removing the need for busdma_swi_pending. One consequence is that the swi now works on RISC-V which had previously failed to invoke busdma_swi from swi_vm. Reviewed by: imp, kib Sponsored by: Netflix Differential Revision: https://reviews.freebsd.org/D33447
75 lines
2.3 KiB
C
75 lines
2.3 KiB
C
/*-
|
|
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
|
|
*
|
|
* Copyright (c) 1998 Doug Rabson
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
* SUCH DAMAGE.
|
|
*
|
|
* $FreeBSD$
|
|
*/
|
|
|
|
#ifndef _MACHINE_MD_VAR_H_
|
|
#define _MACHINE_MD_VAR_H_
|
|
|
|
/*
|
|
* Miscellaneous machine-dependent declarations.
|
|
*/
|
|
|
|
extern char sigcode32[];
|
|
extern int szsigcode32;
|
|
|
|
#ifdef __powerpc64__
|
|
extern char sigcode64[], sigcode64_elfv2[];
|
|
extern int szsigcode64, szsigcode64_elfv2;
|
|
|
|
struct dumperinfo;
|
|
struct minidumpstate;
|
|
int cpu_minidumpsys(struct dumperinfo *, const struct minidumpstate *);
|
|
#endif
|
|
|
|
extern long Maxmem;
|
|
|
|
extern vm_offset_t kstack0;
|
|
extern vm_offset_t kstack0_phys;
|
|
|
|
extern int powerpc_pow_enabled;
|
|
extern int cacheline_size;
|
|
extern int hw_direct_map;
|
|
|
|
void __syncicache(void *, int);
|
|
|
|
int is_physical_memory(vm_offset_t addr);
|
|
int mem_valid(vm_offset_t addr, int len);
|
|
|
|
void decr_init(void);
|
|
void decr_ap_init(void);
|
|
void decr_tc_init(void);
|
|
|
|
void cpu_feature_setup(void);
|
|
void cpu_setup(u_int);
|
|
|
|
struct trapframe;
|
|
void powerpc_interrupt(struct trapframe *);
|
|
|
|
#endif /* !_MACHINE_MD_VAR_H_ */
|