119 lines
4.8 KiB
C
119 lines
4.8 KiB
C
/*-
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: psl.h,v 1.5 2000/11/19 19:52:37 matt Exp $
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PSL_H_
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#define _MACHINE_PSL_H_
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#if defined(E500)
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/*
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* Machine State Register (MSR) - e500 core
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*
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* The PowerPC e500 does not implement the following bits:
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*
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* FP, FE0, FE1 - reserved, always cleared, setting has no effect.
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*
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*/
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#define PSL_UCLE 0x04000000 /* User mode cache lock enable */
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#define PSL_SPE 0x02000000 /* SPE enable */
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#define PSL_WE 0x00040000 /* Wait state enable */
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#define PSL_CE 0x00020000 /* Critical interrupt enable */
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#define PSL_EE 0x00008000 /* External interrupt enable */
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#define PSL_PR 0x00004000 /* User mode */
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#define PSL_FP 0x00002000 /* Floating point available */
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#define PSL_ME 0x00001000 /* Machine check interrupt enable */
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#define PSL_FE0 0x00000800 /* Floating point exception mode 0 */
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#define PSL_UBLE 0x00000400 /* BTB lock enable */
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#define PSL_DE 0x00000200 /* Debug interrupt enable */
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#define PSL_FE1 0x00000100 /* Floating point exception mode 1 */
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#define PSL_IS 0x00000020 /* Instruction address space */
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#define PSL_DS 0x00000010 /* Data address space */
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#define PSL_PMM 0x00000004 /* Performance monitor mark */
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/* Initial kernel MSR, use IS=1 ad DS=1. */
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#define PSL_KERNSET_INIT (PSL_IS | PSL_DS)
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#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE)
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#define PSL_USERSET (PSL_KERNSET | PSL_PR)
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#else /* if defined(E500) */
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/*
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* Machine State Register (MSR)
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*
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* The PowerPC 601 does not implement the following bits:
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*
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* VEC, POW, ILE, BE, RI, LE[*]
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*
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* [*] Little-endian mode on the 601 is implemented in the HID0 register.
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*/
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#define PSL_VEC 0x02000000 /* AltiVec vector unit available */
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#define PSL_POW 0x00040000 /* power management */
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#define PSL_ILE 0x00010000 /* interrupt endian mode (1 == le) */
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#define PSL_EE 0x00008000 /* external interrupt enable */
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#define PSL_PR 0x00004000 /* privilege mode (1 == user) */
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#define PSL_FP 0x00002000 /* floating point enable */
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#define PSL_ME 0x00001000 /* machine check enable */
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#define PSL_FE0 0x00000800 /* floating point interrupt mode 0 */
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#define PSL_SE 0x00000400 /* single-step trace enable */
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#define PSL_BE 0x00000200 /* branch trace enable */
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#define PSL_FE1 0x00000100 /* floating point interrupt mode 1 */
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#define PSL_IP 0x00000040 /* interrupt prefix */
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#define PSL_IR 0x00000020 /* instruction address relocation */
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#define PSL_DR 0x00000010 /* data address relocation */
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#define PSL_RI 0x00000002 /* recoverable interrupt */
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#define PSL_LE 0x00000001 /* endian mode (1 == le) */
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#define PSL_601_MASK ~(PSL_POW|PSL_ILE|PSL_BE|PSL_RI|PSL_LE)
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/*
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* Floating-point exception modes:
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*/
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#define PSL_FE_DIS 0 /* none */
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#define PSL_FE_NONREC PSL_FE1 /* imprecise non-recoverable */
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#define PSL_FE_REC PSL_FE0 /* imprecise recoverable */
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#define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */
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#define PSL_FE_DFLT PSL_FE_DIS /* default == none */
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/*
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* Note that PSL_POW and PSL_ILE are not in the saved copy of the MSR
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*/
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#define PSL_MBO 0
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#define PSL_MBZ 0
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#define PSL_KERNSET (PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI)
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#define PSL_USERSET (PSL_KERNSET | PSL_PR)
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#define PSL_USERSTATIC (PSL_USERSET | PSL_IP | 0x87c0008c)
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#endif /* if defined(E500) */
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#endif /* _MACHINE_PSL_H_ */
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