386 lines
11 KiB
C
386 lines
11 KiB
C
/*-
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* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <arm/ti/ti_prcm.h>
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#define AM335X_NUM_TIMERS 8
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#define DMTIMER_TIDR 0x00 /* Identification Register */
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#define DMTIMER_TIOCP_CFG 0x10 /* Timer OCP Configuration Reg */
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#define DMTIMER_IQR_EOI 0x20 /* Timer IRQ End-Of-Interrupt Reg */
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#define DMTIMER_IRQSTATUS_RAW 0x24 /* Timer IRQSTATUS Raw Reg */
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#define DMTIMER_IRQSTATUS 0x28 /* Timer IRQSTATUS Reg */
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#define DMTIMER_IRQENABLE_SET 0x2c /* Timer IRQSTATUS Set Reg */
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#define DMTIMER_IRQENABLE_CLR 0x30 /* Timer IRQSTATUS Clear Reg */
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#define DMTIMER_IRQWAKEEN 0x34 /* Timer IRQ Wakeup Enable Reg */
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#define DMTIMER_TCLR 0x38 /* Timer Control Register */
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#define DMTIMER_TCRR 0x3C /* Timer Counter Register */
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#define DMTIMER_TLDR 0x40 /* Timer Load Reg */
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#define DMTIMER_TTGR 0x44 /* Timer Trigger Reg */
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#define DMTIMER_TWPS 0x48 /* Timer Write Posted Status Reg */
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#define DMTIMER_TMAR 0x4C /* Timer Match Reg */
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#define DMTIMER_TCAR1 0x50 /* Timer Capture Reg */
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#define DMTIMER_TSICR 0x54 /* Timer Synchr. Interface Control Reg */
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#define DMTIMER_TCAR2 0x48 /* Timer Capture Reg */
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struct am335x_dmtimer_softc {
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struct resource * tmr_mem_res[AM335X_NUM_TIMERS];
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struct resource * tmr_irq_res[AM335X_NUM_TIMERS];
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uint32_t sysclk_freq;
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struct am335x_dmtimer {
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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struct eventtimer et;
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} t[AM335X_NUM_TIMERS];
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};
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static struct resource_spec am335x_dmtimer_mem_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ SYS_RES_MEMORY, 2, RF_ACTIVE },
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{ SYS_RES_MEMORY, 3, RF_ACTIVE },
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{ SYS_RES_MEMORY, 4, RF_ACTIVE },
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{ SYS_RES_MEMORY, 5, RF_ACTIVE },
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{ SYS_RES_MEMORY, 6, RF_ACTIVE },
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{ SYS_RES_MEMORY, 7, RF_ACTIVE },
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{ -1, 0, 0 }
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};
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static struct resource_spec am335x_dmtimer_irq_spec[] = {
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE },
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{ SYS_RES_IRQ, 2, RF_ACTIVE },
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{ SYS_RES_IRQ, 3, RF_ACTIVE },
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{ SYS_RES_IRQ, 4, RF_ACTIVE },
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{ SYS_RES_IRQ, 5, RF_ACTIVE },
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{ SYS_RES_IRQ, 6, RF_ACTIVE },
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{ SYS_RES_IRQ, 7, RF_ACTIVE },
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{ -1, 0, 0 }
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};
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static struct am335x_dmtimer *am335x_dmtimer_tc_tmr = NULL;
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/* Read/Write macros for Timer used as timecounter */
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#define am335x_dmtimer_tc_read_4(reg) \
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bus_space_read_4(am335x_dmtimer_tc_tmr->bst, \
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am335x_dmtimer_tc_tmr->bsh, reg)
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#define am335x_dmtimer_tc_write_4(reg, val) \
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bus_space_write_4(am335x_dmtimer_tc_tmr->bst, \
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am335x_dmtimer_tc_tmr->bsh, reg, val)
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/* Read/Write macros for Timer used as eventtimer */
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#define am335x_dmtimer_et_read_4(reg) \
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bus_space_read_4(tmr->bst, tmr->bsh, reg)
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#define am335x_dmtimer_et_write_4(reg, val) \
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bus_space_write_4(tmr->bst, tmr->bsh, reg, val)
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static unsigned am335x_dmtimer_tc_get_timecount(struct timecounter *);
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static struct timecounter am335x_dmtimer_tc = {
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.tc_name = "AM335x Timecounter",
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.tc_get_timecount = am335x_dmtimer_tc_get_timecount,
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.tc_poll_pps = NULL,
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.tc_counter_mask = ~0u,
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.tc_frequency = 0,
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.tc_quality = 1000,
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};
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static unsigned
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am335x_dmtimer_tc_get_timecount(struct timecounter *tc)
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{
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return am335x_dmtimer_tc_read_4(DMTIMER_TCRR);
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}
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static int
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am335x_dmtimer_start(struct eventtimer *et, struct bintime *first,
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struct bintime *period)
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{
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struct am335x_dmtimer *tmr = (struct am335x_dmtimer *)et->et_priv;
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uint32_t load, count;
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uint32_t tclr = 0;
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if (period != NULL) {
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load = (et->et_frequency * (period->frac >> 32)) >> 32;
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if (period->sec > 0)
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load += et->et_frequency * period->sec;
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tclr |= 2; /* autoreload bit */
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panic("periodic timer not implemented\n");
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} else {
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load = 0;
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}
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if (first != NULL) {
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count = (tmr->et.et_frequency * (first->frac >> 32)) >> 32;
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if (first->sec != 0)
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count += tmr->et.et_frequency * first->sec;
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} else {
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count = load;
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}
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/* Reset Timer */
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am335x_dmtimer_et_write_4(DMTIMER_TSICR, 2);
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/* Wait for reset to complete */
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while (am335x_dmtimer_et_read_4(DMTIMER_TIOCP_CFG) & 1);
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/* set load value */
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am335x_dmtimer_et_write_4(DMTIMER_TLDR, 0xFFFFFFFE - load);
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/* set counter value */
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am335x_dmtimer_et_write_4(DMTIMER_TCRR, 0xFFFFFFFE - count);
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/* enable overflow interrupt */
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am335x_dmtimer_et_write_4(DMTIMER_IRQENABLE_SET, 2);
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/* start timer(ST) */
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tclr |= 1;
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am335x_dmtimer_et_write_4(DMTIMER_TCLR, tclr);
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return (0);
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}
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static int
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am335x_dmtimer_stop(struct eventtimer *et)
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{
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struct am335x_dmtimer *tmr = (struct am335x_dmtimer *)et->et_priv;
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/* Disable all interrupts */
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am335x_dmtimer_et_write_4(DMTIMER_IRQENABLE_CLR, 7);
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/* Stop Timer */
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am335x_dmtimer_et_write_4(DMTIMER_TCLR, 0);
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return (0);
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}
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static int
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am335x_dmtimer_intr(void *arg)
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{
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struct am335x_dmtimer *tmr = (struct am335x_dmtimer *)arg;
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/* Ack interrupt */
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am335x_dmtimer_et_write_4(DMTIMER_IRQSTATUS, 7);
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if (tmr->et.et_active)
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tmr->et.et_event_cb(&tmr->et, tmr->et.et_arg);
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return (FILTER_HANDLED);
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}
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static int
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am335x_dmtimer_probe(device_t dev)
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{
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struct am335x_dmtimer_softc *sc;
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sc = (struct am335x_dmtimer_softc *)device_get_softc(dev);
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if (ofw_bus_is_compatible(dev, "ti,am335x-dmtimer")) {
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device_set_desc(dev, "AM335x DMTimer");
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return(BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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am335x_dmtimer_attach(device_t dev)
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{
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struct am335x_dmtimer_softc *sc = device_get_softc(dev);
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void *ihl;
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int err;
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int i;
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if (am335x_dmtimer_tc_tmr != NULL)
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return (EINVAL);
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/* Get the base clock frequency */
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err = ti_prcm_clk_get_source_freq(SYS_CLK, &sc->sysclk_freq);
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if (err) {
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device_printf(dev, "Error: could not get sysclk frequency\n");
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return (ENXIO);
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}
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/* Request the memory resources */
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err = bus_alloc_resources(dev, am335x_dmtimer_mem_spec,
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sc->tmr_mem_res);
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if (err) {
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device_printf(dev, "Error: could not allocate mem resources\n");
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return (ENXIO);
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}
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/* Request the IRQ resources */
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err = bus_alloc_resources(dev, am335x_dmtimer_irq_spec,
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sc->tmr_irq_res);
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if (err) {
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device_printf(dev, "Error: could not allocate irq resources\n");
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return (ENXIO);
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}
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for(i=0;i<AM335X_NUM_TIMERS;i++) {
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sc->t[i].bst = rman_get_bustag(sc->tmr_mem_res[i]);
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sc->t[i].bsh = rman_get_bushandle(sc->tmr_mem_res[i]);
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}
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/* Configure DMTimer2 and DMTimer3 source and enable them */
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err = ti_prcm_clk_set_source(DMTIMER2_CLK, SYSCLK_CLK);
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err |= ti_prcm_clk_enable(DMTIMER2_CLK);
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err |= ti_prcm_clk_set_source(DMTIMER3_CLK, SYSCLK_CLK);
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err |= ti_prcm_clk_enable(DMTIMER3_CLK);
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if (err) {
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device_printf(dev, "Error: could not setup timer clock\n");
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return (ENXIO);
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}
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/* Take DMTimer2 for TC */
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am335x_dmtimer_tc_tmr = &sc->t[2];
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/* Reset Timer */
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am335x_dmtimer_tc_write_4(DMTIMER_TSICR, 2);
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/* Wait for reset to complete */
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while (am335x_dmtimer_tc_read_4(DMTIMER_TIOCP_CFG) & 1);
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/* set load value */
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am335x_dmtimer_tc_write_4(DMTIMER_TLDR, 0);
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/* set counter value */
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am335x_dmtimer_tc_write_4(DMTIMER_TCRR, 0);
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/* Set Timer autoreload(AR) and start timer(ST) */
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am335x_dmtimer_tc_write_4(DMTIMER_TCLR, 3);
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am335x_dmtimer_tc.tc_frequency = sc->sysclk_freq;
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tc_init(&am335x_dmtimer_tc);
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/* Register DMTimer3 as ET */
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/* Setup and enable the timer */
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if (bus_setup_intr(dev, sc->tmr_irq_res[3], INTR_TYPE_CLK,
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am335x_dmtimer_intr, NULL, &sc->t[3], &ihl) != 0) {
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bus_release_resources(dev, am335x_dmtimer_irq_spec,
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sc->tmr_irq_res);
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device_printf(dev, "Unable to setup the clock irq handler.\n");
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return (ENXIO);
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}
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sc->t[3].et.et_name = "AM335x Eventtimer0";
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sc->t[3].et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
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sc->t[3].et.et_quality = 1000;
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sc->t[3].et.et_frequency = sc->sysclk_freq;
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sc->t[3].et.et_min_period.sec = 0;
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sc->t[3].et.et_min_period.frac =
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((0x00000002LLU << 32) / sc->t[3].et.et_frequency) << 32;
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sc->t[3].et.et_max_period.sec = 0xfffffff0U / sc->t[3].et.et_frequency;
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sc->t[3].et.et_max_period.frac =
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((0xfffffffeLLU << 32) / sc->t[3].et.et_frequency) << 32;
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sc->t[3].et.et_start = am335x_dmtimer_start;
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sc->t[3].et.et_stop = am335x_dmtimer_stop;
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sc->t[3].et.et_priv = &sc->t[3];
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et_register(&sc->t[3].et);
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return (0);
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}
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static device_method_t am335x_dmtimer_methods[] = {
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DEVMETHOD(device_probe, am335x_dmtimer_probe),
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DEVMETHOD(device_attach, am335x_dmtimer_attach),
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{ 0, 0 }
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};
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static driver_t am335x_dmtimer_driver = {
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"am335x_dmtimer",
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am335x_dmtimer_methods,
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sizeof(struct am335x_dmtimer_softc),
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};
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static devclass_t am335x_dmtimer_devclass;
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DRIVER_MODULE(am335x_dmtimer, simplebus, am335x_dmtimer_driver, am335x_dmtimer_devclass, 0, 0);
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MODULE_DEPEND(am335x_dmtimer, am335x_prcm, 1, 1, 1);
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void
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cpu_initclocks(void)
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{
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cpu_initclocks_bsp();
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}
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void
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DELAY(int usec)
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{
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int32_t counts;
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uint32_t first, last;
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if (am335x_dmtimer_tc_tmr == NULL) {
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for (; usec > 0; usec--)
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for (counts = 200; counts > 0; counts--)
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/* Prevent gcc from optimizing out the loop */
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cpufunc_nullop();
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return;
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}
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/* Get the number of times to count */
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counts = usec * ((am335x_dmtimer_tc.tc_frequency / 1000000) + 1);
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first = am335x_dmtimer_tc_read_4(DMTIMER_TCRR);
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while (counts > 0) {
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last = am335x_dmtimer_tc_read_4(DMTIMER_TCRR);
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if (last>first) {
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counts -= (int32_t)(last - first);
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} else {
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counts -= (int32_t)((0xFFFFFFFF - first) + last);
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}
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first = last;
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}
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}
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