246 lines
6.9 KiB
C
246 lines
6.9 KiB
C
/*-
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* Copyright (c) 2017 Andriy Gapon
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/conf.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/sysctl.h>
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#include <sys/types.h>
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#include <dev/pci/pcivar.h>
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#include <vm/vm.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_kern.h>
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#include <machine/cputypes.h>
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#include <machine/md_var.h>
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/*
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* See BKDG for AMD Family 15h Models 00h-0Fh Processors
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* (publication 42301 Rev 3.08 - March 12, 2012):
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* - 2.13.3.1 DRAM Error Injection
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* - D18F3xB8 NB Array Address
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* - D18F3xBC NB Array Data Port
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* - D18F3xBC_x8 DRAM ECC
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*/
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#define NB_MCA_CFG 0x44
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#define DRAM_ECC_EN (1 << 22)
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#define NB_MCA_EXTCFG 0x180
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#define ECC_SYMB_SZ (1 << 25)
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#define NB_ARRAY_ADDR 0xb8
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#define DRAM_ECC_SEL (0x8 << 28)
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#define QUADRANT_SHIFT 1
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#define QUADRANT_MASK 0x3
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#define NB_ARRAY_PORT 0xbc
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#define INJ_WORD_SHIFT 20
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#define INJ_WORD_MASK 0x1ff
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#define DRAM_ERR_EN (1 << 18)
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#define DRAM_WR_REQ (1 << 17)
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#define DRAM_RD_REQ (1 << 16)
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#define INJ_VECTOR_MASK 0xffff
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static void ecc_ei_inject(int);
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static device_t nbdev;
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static int delay_ms = 0;
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static int quadrant = 0; /* 0 - 3 */
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static int word_mask = 0x001; /* 9 bits: 8 + 1 for ECC */
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static int bit_mask = 0x0001; /* 16 bits */
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static int
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sysctl_int_with_max(SYSCTL_HANDLER_ARGS)
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{
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u_int value;
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int error;
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value = *(u_int *)arg1;
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error = sysctl_handle_int(oidp, &value, 0, req);
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if (error || req->newptr == NULL)
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return (error);
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if (value > arg2)
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return (EINVAL);
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*(u_int *)arg1 = value;
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return (0);
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}
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static int
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sysctl_nonzero_int_with_max(SYSCTL_HANDLER_ARGS)
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{
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u_int value;
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int error;
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value = *(u_int *)arg1;
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error = sysctl_int_with_max(oidp, &value, arg2, req);
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if (error || req->newptr == NULL)
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return (error);
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if (value == 0)
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return (EINVAL);
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*(u_int *)arg1 = value;
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return (0);
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}
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static int
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sysctl_proc_inject(SYSCTL_HANDLER_ARGS)
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{
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int error;
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int i;
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i = 0;
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error = sysctl_handle_int(oidp, &i, 0, req);
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if (error)
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return (error);
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if (i != 0)
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ecc_ei_inject(i);
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return (0);
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}
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static SYSCTL_NODE(_hw, OID_AUTO, error_injection,
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CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
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"Hardware error injection");
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static SYSCTL_NODE(_hw_error_injection, OID_AUTO, dram_ecc,
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CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
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"DRAM ECC error injection");
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SYSCTL_UINT(_hw_error_injection_dram_ecc, OID_AUTO, delay,
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CTLTYPE_UINT | CTLFLAG_RW, &delay_ms, 0,
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"Delay in milliseconds between error injections");
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SYSCTL_PROC(_hw_error_injection_dram_ecc, OID_AUTO, quadrant,
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CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &quadrant, QUADRANT_MASK,
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sysctl_int_with_max, "IU",
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"Index of 16-byte quadrant within 64-byte line where errors "
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"should be injected");
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SYSCTL_PROC(_hw_error_injection_dram_ecc, OID_AUTO, word_mask,
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CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &word_mask, INJ_WORD_MASK,
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sysctl_nonzero_int_with_max, "IU",
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"9-bit mask of words where errors should be injected (8 data + 1 ECC)");
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SYSCTL_PROC(_hw_error_injection_dram_ecc, OID_AUTO, bit_mask,
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CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &bit_mask, INJ_VECTOR_MASK,
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sysctl_nonzero_int_with_max, "IU",
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"16-bit mask of bits within each selected word where errors "
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"should be injected");
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SYSCTL_PROC(_hw_error_injection_dram_ecc, OID_AUTO, inject,
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CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 0, sysctl_proc_inject, "I",
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"Inject a number of errors according to configured parameters");
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static void
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ecc_ei_inject_one(void *arg, size_t size)
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{
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volatile uint64_t *memory = arg;
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uint32_t val;
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int i;
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val = DRAM_ECC_SEL | (quadrant << QUADRANT_SHIFT);
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pci_write_config(nbdev, NB_ARRAY_ADDR, val, 4);
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val = (word_mask << INJ_WORD_SHIFT) | DRAM_WR_REQ | bit_mask;
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pci_write_config(nbdev, NB_ARRAY_PORT, val, 4);
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for (i = 0; i < size / sizeof(uint64_t); i++) {
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memory[i] = 0;
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val = pci_read_config(nbdev, NB_ARRAY_PORT, 4);
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if ((val & DRAM_WR_REQ) == 0)
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break;
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}
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for (i = 0; i < size / sizeof(uint64_t); i++)
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memory[0] = memory[i];
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}
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static void
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ecc_ei_inject(int count)
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{
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vm_offset_t memory;
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int injected;
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KASSERT((quadrant & ~QUADRANT_MASK) == 0,
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("quadrant value is outside of range: %u", quadrant));
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KASSERT(word_mask != 0 && (word_mask & ~INJ_WORD_MASK) == 0,
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("word mask value is outside of range: 0x%x", word_mask));
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KASSERT(bit_mask != 0 && (bit_mask & ~INJ_VECTOR_MASK) == 0,
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("bit mask value is outside of range: 0x%x", bit_mask));
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memory = kmem_alloc_attr(PAGE_SIZE, M_WAITOK, 0, ~0,
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VM_MEMATTR_UNCACHEABLE);
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for (injected = 0; injected < count; injected++) {
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ecc_ei_inject_one((void*)memory, PAGE_SIZE);
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if (delay_ms != 0 && injected != count - 1)
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pause_sbt("ecc_ei_inject", delay_ms * SBT_1MS, 0, 0);
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}
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kmem_free(memory, PAGE_SIZE);
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}
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static int
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ecc_ei_load(void)
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{
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uint32_t val;
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if ((cpu_vendor_id != CPU_VENDOR_AMD || CPUID_TO_FAMILY(cpu_id) < 0x10) &&
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cpu_vendor_id != CPU_VENDOR_HYGON) {
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printf("DRAM ECC error injection is not supported\n");
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return (ENXIO);
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}
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nbdev = pci_find_bsf(0, 24, 3);
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if (nbdev == NULL) {
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printf("Couldn't find NB PCI device\n");
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return (ENXIO);
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}
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val = pci_read_config(nbdev, NB_MCA_CFG, 4);
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if ((val & DRAM_ECC_EN) == 0) {
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printf("DRAM ECC is not supported or disabled\n");
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return (ENXIO);
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}
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printf("DRAM ECC error injection support loaded\n");
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return (0);
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}
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static int
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tsc_modevent(module_t mod __unused, int type, void *data __unused)
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{
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int error;
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error = 0;
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switch (type) {
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case MOD_LOAD:
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error = ecc_ei_load();
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break;
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case MOD_UNLOAD:
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case MOD_SHUTDOWN:
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break;
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default:
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error = EOPNOTSUPP;
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}
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return (error);
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}
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DEV_MODULE(tsc, tsc_modevent, NULL);
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