51dbd04609
static device mappings. This SoC relied heavily on the fact that all devices were static-mapped at a fixed address, and it (rather bogusly) used bus_space read and write calls passing hard-coded virtual addresses instead of proper bus handles, relying on the fact that the virtual addresses of the mappings were known at compile time, and relying on the implementation details of arm bus_space never changing. All such usage was replaced with calls to bus_space_map() to obtain a proper bus handle for the read/write calls. This required adjusting some of the #define values that map out hardware registers, and some of them were renamed in the process to make it clear which were defining absolute physical addresses and which were defining offsets. (The ones that just define offsets don't appear to be referenced and probably serve no value other than perhaps documentation.)
893 lines
21 KiB
C
893 lines
21 KiB
C
/*-
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* Copyright (c) 2003 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include <dev/ic/ns16550.h>
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#include <arm/lpc/lpcreg.h>
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#include "uart_if.h"
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#define DEFAULT_RCLK (13 * 1000 * 1000)
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static bus_space_handle_t bsh_clkpwr;
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#define lpc_ns8250_get_clkreg(_bas, _reg) \
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bus_space_read_4(fdtbus_bs_tag, bsh_clkpwr, (_reg))
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#define lpc_ns8250_set_clkreg(_bas, _reg, _val) \
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bus_space_write_4(fdtbus_bs_tag, bsh_clkpwr, (_reg), (_val))
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/*
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* Clear pending interrupts. THRE is cleared by reading IIR. Data
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* that may have been received gets lost here.
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*/
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static void
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lpc_ns8250_clrint(struct uart_bas *bas)
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{
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uint8_t iir, lsr;
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iir = uart_getreg(bas, REG_IIR);
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while ((iir & IIR_NOPEND) == 0) {
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iir &= IIR_IMASK;
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if (iir == IIR_RLS) {
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lsr = uart_getreg(bas, REG_LSR);
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if (lsr & (LSR_BI|LSR_FE|LSR_PE))
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(void)uart_getreg(bas, REG_DATA);
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} else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
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(void)uart_getreg(bas, REG_DATA);
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else if (iir == IIR_MLSC)
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(void)uart_getreg(bas, REG_MSR);
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uart_barrier(bas);
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iir = uart_getreg(bas, REG_IIR);
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}
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}
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static int
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lpc_ns8250_delay(struct uart_bas *bas)
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{
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uint32_t uclk;
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int x, y;
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uclk = lpc_ns8250_get_clkreg(bas, LPC_CLKPWR_UART_U5CLK);
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x = (uclk >> 8) & 0xff;
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y = uclk & 0xff;
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return (16000000 / (bas->rclk * x / y));
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}
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static void
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lpc_ns8250_divisor(int rclk, int baudrate, int *x, int *y)
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{
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switch (baudrate) {
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case 2400:
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*x = 1;
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*y = 255;
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return;
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case 4800:
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*x = 1;
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*y = 169;
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return;
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case 9600:
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*x = 3;
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*y = 254;
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return;
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case 19200:
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*x = 3;
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*y = 127;
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return;
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case 38400:
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*x = 6;
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*y = 127;
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return;
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case 57600:
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*x = 9;
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*y = 127;
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return;
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default:
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case 115200:
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*x = 19;
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*y = 134;
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return;
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case 230400:
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*x = 19;
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*y = 67;
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return;
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case 460800:
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*x = 38;
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*y = 67;
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return;
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}
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}
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static int
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lpc_ns8250_drain(struct uart_bas *bas, int what)
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{
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int delay, limit;
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delay = lpc_ns8250_delay(bas);
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if (what & UART_DRAIN_TRANSMITTER) {
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/*
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* Pick an arbitrary high limit to avoid getting stuck in
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* an infinite loop when the hardware is broken. Make the
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* limit high enough to handle large FIFOs.
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*/
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limit = 10*1024;
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while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
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DELAY(delay);
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if (limit == 0) {
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/* printf("lpc_ns8250: transmitter appears stuck... "); */
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return (EIO);
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}
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}
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if (what & UART_DRAIN_RECEIVER) {
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/*
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* Pick an arbitrary high limit to avoid getting stuck in
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* an infinite loop when the hardware is broken. Make the
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* limit high enough to handle large FIFOs and integrated
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* UARTs. The HP rx2600 for example has 3 UARTs on the
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* management board that tend to get a lot of data send
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* to it when the UART is first activated.
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*/
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limit=10*4096;
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while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
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(void)uart_getreg(bas, REG_DATA);
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uart_barrier(bas);
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DELAY(delay << 2);
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}
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if (limit == 0) {
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/* printf("lpc_ns8250: receiver appears broken... "); */
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return (EIO);
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}
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}
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return (0);
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}
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/*
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* We can only flush UARTs with FIFOs. UARTs without FIFOs should be
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* drained. WARNING: this function clobbers the FIFO setting!
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*/
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static void
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lpc_ns8250_flush(struct uart_bas *bas, int what)
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{
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uint8_t fcr;
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fcr = FCR_ENABLE;
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if (what & UART_FLUSH_TRANSMITTER)
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fcr |= FCR_XMT_RST;
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if (what & UART_FLUSH_RECEIVER)
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fcr |= FCR_RCV_RST;
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uart_setreg(bas, REG_FCR, fcr);
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uart_barrier(bas);
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}
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static int
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lpc_ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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int xdiv, ydiv;
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uint8_t lcr;
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lcr = 0;
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if (databits >= 8)
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lcr |= LCR_8BITS;
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else if (databits == 7)
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lcr |= LCR_7BITS;
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else if (databits == 6)
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lcr |= LCR_6BITS;
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else
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lcr |= LCR_5BITS;
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if (stopbits > 1)
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lcr |= LCR_STOPB;
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lcr |= parity << 3;
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/* Set baudrate. */
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if (baudrate > 0) {
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uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
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uart_barrier(bas);
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uart_setreg(bas, REG_DLL, 0x00);
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uart_setreg(bas, REG_DLH, 0x00);
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uart_barrier(bas);
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lpc_ns8250_divisor(bas->rclk, baudrate, &xdiv, &ydiv);
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lpc_ns8250_set_clkreg(bas,
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LPC_CLKPWR_UART_U5CLK,
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LPC_CLKPWR_UART_UCLK_X(xdiv) |
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LPC_CLKPWR_UART_UCLK_Y(ydiv));
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}
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/* Set LCR and clear DLAB. */
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uart_setreg(bas, REG_LCR, lcr);
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uart_barrier(bas);
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return (0);
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}
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/*
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* Low-level UART interface.
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*/
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static int lpc_ns8250_probe(struct uart_bas *bas);
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static void lpc_ns8250_init(struct uart_bas *bas, int, int, int, int);
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static void lpc_ns8250_term(struct uart_bas *bas);
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static void lpc_ns8250_putc(struct uart_bas *bas, int);
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static int lpc_ns8250_rxready(struct uart_bas *bas);
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static int lpc_ns8250_getc(struct uart_bas *bas, struct mtx *);
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static struct uart_ops uart_lpc_ns8250_ops = {
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.probe = lpc_ns8250_probe,
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.init = lpc_ns8250_init,
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.term = lpc_ns8250_term,
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.putc = lpc_ns8250_putc,
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.rxready = lpc_ns8250_rxready,
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.getc = lpc_ns8250_getc,
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};
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static int
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lpc_ns8250_probe(struct uart_bas *bas)
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{
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#if 0
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u_char val;
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/* Check known 0 bits that don't depend on DLAB. */
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val = uart_getreg(bas, REG_IIR);
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if (val & 0x30)
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return (ENXIO);
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/*
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* Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
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* chip, but otherwise doesn't seem to have a function. In
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* other words, uart(4) works regardless. Ignore that bit so
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* the probe succeeds.
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*/
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val = uart_getreg(bas, REG_MCR);
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if (val & 0xa0)
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return (ENXIO);
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#endif
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return (0);
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}
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static void
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lpc_ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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u_char ier;
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u_long clkmode;
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/* Enable UART clock */
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bus_space_map(fdtbus_bs_tag, LPC_CLKPWR_PHYS_BASE, LPC_CLKPWR_SIZE, 0,
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&bsh_clkpwr);
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clkmode = lpc_ns8250_get_clkreg(bas, LPC_UART_CLKMODE);
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lpc_ns8250_set_clkreg(bas, LPC_UART_CLKMODE, clkmode |
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LPC_UART_CLKMODE_UART5(1));
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#if 0
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/* Work around H/W bug */
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uart_setreg(bas, REG_DATA, 0x00);
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#endif
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if (bas->rclk == 0)
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bas->rclk = DEFAULT_RCLK;
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lpc_ns8250_param(bas, baudrate, databits, stopbits, parity);
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/* Disable all interrupt sources. */
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/*
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* We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
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* UARTs split the receive time-out interrupt bit out separately as
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* 0x10. This gets handled by ier_mask and ier_rxbits below.
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*/
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ier = uart_getreg(bas, REG_IER) & 0xe0;
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uart_setreg(bas, REG_IER, ier);
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uart_barrier(bas);
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/* Disable the FIFO (if present). */
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uart_setreg(bas, REG_FCR, 0);
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uart_barrier(bas);
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/* Set RTS & DTR. */
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uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
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uart_barrier(bas);
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lpc_ns8250_clrint(bas);
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}
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static void
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lpc_ns8250_term(struct uart_bas *bas)
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{
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/* Clear RTS & DTR. */
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uart_setreg(bas, REG_MCR, MCR_IE);
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uart_barrier(bas);
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}
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static void
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lpc_ns8250_putc(struct uart_bas *bas, int c)
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{
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int limit;
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limit = 250000;
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while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
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DELAY(4);
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uart_setreg(bas, REG_DATA, c);
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uart_barrier(bas);
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limit = 250000;
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while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
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DELAY(4);
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}
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static int
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lpc_ns8250_rxready(struct uart_bas *bas)
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{
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return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
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}
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static int
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lpc_ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
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{
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int c;
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uart_lock(hwmtx);
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while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
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uart_unlock(hwmtx);
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DELAY(4);
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uart_lock(hwmtx);
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}
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c = uart_getreg(bas, REG_DATA);
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uart_unlock(hwmtx);
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return (c);
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}
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/*
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* High-level UART interface.
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*/
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struct lpc_ns8250_softc {
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struct uart_softc base;
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uint8_t fcr;
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uint8_t ier;
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uint8_t mcr;
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uint8_t ier_mask;
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uint8_t ier_rxbits;
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};
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static int lpc_ns8250_bus_attach(struct uart_softc *);
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static int lpc_ns8250_bus_detach(struct uart_softc *);
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static int lpc_ns8250_bus_flush(struct uart_softc *, int);
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static int lpc_ns8250_bus_getsig(struct uart_softc *);
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static int lpc_ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int lpc_ns8250_bus_ipend(struct uart_softc *);
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static int lpc_ns8250_bus_param(struct uart_softc *, int, int, int, int);
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static int lpc_ns8250_bus_probe(struct uart_softc *);
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static int lpc_ns8250_bus_receive(struct uart_softc *);
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static int lpc_ns8250_bus_setsig(struct uart_softc *, int);
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static int lpc_ns8250_bus_transmit(struct uart_softc *);
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static kobj_method_t lpc_ns8250_methods[] = {
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KOBJMETHOD(uart_attach, lpc_ns8250_bus_attach),
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KOBJMETHOD(uart_detach, lpc_ns8250_bus_detach),
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KOBJMETHOD(uart_flush, lpc_ns8250_bus_flush),
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KOBJMETHOD(uart_getsig, lpc_ns8250_bus_getsig),
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KOBJMETHOD(uart_ioctl, lpc_ns8250_bus_ioctl),
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KOBJMETHOD(uart_ipend, lpc_ns8250_bus_ipend),
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KOBJMETHOD(uart_param, lpc_ns8250_bus_param),
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KOBJMETHOD(uart_probe, lpc_ns8250_bus_probe),
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KOBJMETHOD(uart_receive, lpc_ns8250_bus_receive),
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KOBJMETHOD(uart_setsig, lpc_ns8250_bus_setsig),
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KOBJMETHOD(uart_transmit, lpc_ns8250_bus_transmit),
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{ 0, 0 }
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};
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struct uart_class uart_lpc_class = {
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"lpc_ns8250",
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lpc_ns8250_methods,
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sizeof(struct lpc_ns8250_softc),
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.uc_ops = &uart_lpc_ns8250_ops,
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.uc_range = 8,
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.uc_rclk = DEFAULT_RCLK
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};
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#define SIGCHG(c, i, s, d) \
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if (c) { \
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i |= (i & s) ? s : s | d; \
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} else { \
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i = (i & s) ? (i & ~s) | d : i; \
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}
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static int
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lpc_ns8250_bus_attach(struct uart_softc *sc)
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{
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struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
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struct uart_bas *bas;
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unsigned int ivar;
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bas = &sc->sc_bas;
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lpc_ns8250->mcr = uart_getreg(bas, REG_MCR);
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lpc_ns8250->fcr = FCR_ENABLE | FCR_DMA;
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if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
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&ivar)) {
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if (UART_FLAGS_FCR_RX_LOW(ivar))
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lpc_ns8250->fcr |= FCR_RX_LOW;
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else if (UART_FLAGS_FCR_RX_MEDL(ivar))
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lpc_ns8250->fcr |= FCR_RX_MEDL;
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else if (UART_FLAGS_FCR_RX_HIGH(ivar))
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lpc_ns8250->fcr |= FCR_RX_HIGH;
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else
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lpc_ns8250->fcr |= FCR_RX_MEDH;
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} else
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lpc_ns8250->fcr |= FCR_RX_HIGH;
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/* Get IER mask */
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ivar = 0xf0;
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resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
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&ivar);
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lpc_ns8250->ier_mask = (uint8_t)(ivar & 0xff);
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/* Get IER RX interrupt bits */
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ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
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resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
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&ivar);
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lpc_ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
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uart_setreg(bas, REG_FCR, lpc_ns8250->fcr);
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uart_barrier(bas);
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lpc_ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
|
|
|
|
if (lpc_ns8250->mcr & MCR_DTR)
|
|
sc->sc_hwsig |= SER_DTR;
|
|
if (lpc_ns8250->mcr & MCR_RTS)
|
|
sc->sc_hwsig |= SER_RTS;
|
|
lpc_ns8250_bus_getsig(sc);
|
|
|
|
lpc_ns8250_clrint(bas);
|
|
lpc_ns8250->ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
|
|
lpc_ns8250->ier |= lpc_ns8250->ier_rxbits;
|
|
uart_setreg(bas, REG_IER, lpc_ns8250->ier);
|
|
uart_barrier(bas);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
lpc_ns8250_bus_detach(struct uart_softc *sc)
|
|
{
|
|
struct lpc_ns8250_softc *lpc_ns8250;
|
|
struct uart_bas *bas;
|
|
u_char ier;
|
|
|
|
lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
|
|
bas = &sc->sc_bas;
|
|
ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
|
|
uart_setreg(bas, REG_IER, ier);
|
|
uart_barrier(bas);
|
|
lpc_ns8250_clrint(bas);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
lpc_ns8250_bus_flush(struct uart_softc *sc, int what)
|
|
{
|
|
struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
|
|
struct uart_bas *bas;
|
|
int error;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
if (sc->sc_rxfifosz > 1) {
|
|
lpc_ns8250_flush(bas, what);
|
|
uart_setreg(bas, REG_FCR, lpc_ns8250->fcr);
|
|
uart_barrier(bas);
|
|
error = 0;
|
|
} else
|
|
error = lpc_ns8250_drain(bas, what);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
lpc_ns8250_bus_getsig(struct uart_softc *sc)
|
|
{
|
|
uint32_t new, old, sig;
|
|
uint8_t msr;
|
|
|
|
do {
|
|
old = sc->sc_hwsig;
|
|
sig = old;
|
|
uart_lock(sc->sc_hwmtx);
|
|
msr = uart_getreg(&sc->sc_bas, REG_MSR);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
|
|
SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
|
|
SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
|
|
SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
|
|
new = sig & ~SER_MASK_DELTA;
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
return (sig);
|
|
}
|
|
|
|
static int
|
|
lpc_ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
|
|
{
|
|
struct uart_bas *bas;
|
|
int baudrate, divisor, error;
|
|
uint8_t efr, lcr;
|
|
|
|
bas = &sc->sc_bas;
|
|
error = 0;
|
|
uart_lock(sc->sc_hwmtx);
|
|
switch (request) {
|
|
case UART_IOCTL_BREAK:
|
|
lcr = uart_getreg(bas, REG_LCR);
|
|
if (data)
|
|
lcr |= LCR_SBREAK;
|
|
else
|
|
lcr &= ~LCR_SBREAK;
|
|
uart_setreg(bas, REG_LCR, lcr);
|
|
uart_barrier(bas);
|
|
break;
|
|
case UART_IOCTL_IFLOW:
|
|
lcr = uart_getreg(bas, REG_LCR);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, 0xbf);
|
|
uart_barrier(bas);
|
|
efr = uart_getreg(bas, REG_EFR);
|
|
if (data)
|
|
efr |= EFR_RTS;
|
|
else
|
|
efr &= ~EFR_RTS;
|
|
uart_setreg(bas, REG_EFR, efr);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, lcr);
|
|
uart_barrier(bas);
|
|
break;
|
|
case UART_IOCTL_OFLOW:
|
|
lcr = uart_getreg(bas, REG_LCR);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, 0xbf);
|
|
uart_barrier(bas);
|
|
efr = uart_getreg(bas, REG_EFR);
|
|
if (data)
|
|
efr |= EFR_CTS;
|
|
else
|
|
efr &= ~EFR_CTS;
|
|
uart_setreg(bas, REG_EFR, efr);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, lcr);
|
|
uart_barrier(bas);
|
|
break;
|
|
case UART_IOCTL_BAUD:
|
|
lcr = uart_getreg(bas, REG_LCR);
|
|
uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
|
|
uart_barrier(bas);
|
|
divisor = uart_getreg(bas, REG_DLL) |
|
|
(uart_getreg(bas, REG_DLH) << 8);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, lcr);
|
|
uart_barrier(bas);
|
|
baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
|
|
if (baudrate > 0)
|
|
*(int*)data = baudrate;
|
|
else
|
|
error = ENXIO;
|
|
break;
|
|
default:
|
|
error = EINVAL;
|
|
break;
|
|
}
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
lpc_ns8250_bus_ipend(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
struct lpc_ns8250_softc *lpc_ns8250;
|
|
int ipend;
|
|
uint8_t iir, lsr;
|
|
|
|
lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
iir = uart_getreg(bas, REG_IIR);
|
|
if (iir & IIR_NOPEND) {
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
ipend = 0;
|
|
if (iir & IIR_RXRDY) {
|
|
lsr = uart_getreg(bas, REG_LSR);
|
|
if (lsr & LSR_OE)
|
|
ipend |= SER_INT_OVERRUN;
|
|
if (lsr & LSR_BI)
|
|
ipend |= SER_INT_BREAK;
|
|
if (lsr & LSR_RXRDY)
|
|
ipend |= SER_INT_RXREADY;
|
|
} else {
|
|
if (iir & IIR_TXRDY) {
|
|
ipend |= SER_INT_TXIDLE;
|
|
uart_setreg(bas, REG_IER, lpc_ns8250->ier);
|
|
} else
|
|
ipend |= SER_INT_SIGCHG;
|
|
}
|
|
if (ipend == 0)
|
|
lpc_ns8250_clrint(bas);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (ipend);
|
|
}
|
|
|
|
static int
|
|
lpc_ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
|
|
int stopbits, int parity)
|
|
{
|
|
struct uart_bas *bas;
|
|
int error;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
error = lpc_ns8250_param(bas, baudrate, databits, stopbits, parity);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
lpc_ns8250_bus_probe(struct uart_softc *sc)
|
|
{
|
|
struct lpc_ns8250_softc *lpc_ns8250;
|
|
struct uart_bas *bas;
|
|
int count, delay, error, limit;
|
|
uint8_t lsr, mcr, ier;
|
|
|
|
lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
|
|
bas = &sc->sc_bas;
|
|
|
|
error = lpc_ns8250_probe(bas);
|
|
if (error)
|
|
return (error);
|
|
|
|
mcr = MCR_IE;
|
|
if (sc->sc_sysdev == NULL) {
|
|
/* By using lpc_ns8250_init() we also set DTR and RTS. */
|
|
lpc_ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
|
|
} else
|
|
mcr |= MCR_DTR | MCR_RTS;
|
|
|
|
error = lpc_ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
|
|
if (error)
|
|
return (error);
|
|
|
|
/*
|
|
* Set loopback mode. This avoids having garbage on the wire and
|
|
* also allows us send and receive data. We set DTR and RTS to
|
|
* avoid the possibility that automatic flow-control prevents
|
|
* any data from being sent.
|
|
*/
|
|
uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
|
|
uart_barrier(bas);
|
|
|
|
/*
|
|
* Enable FIFOs. And check that the UART has them. If not, we're
|
|
* done. Since this is the first time we enable the FIFOs, we reset
|
|
* them.
|
|
*/
|
|
uart_setreg(bas, REG_FCR, FCR_ENABLE);
|
|
uart_barrier(bas);
|
|
if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
|
|
/*
|
|
* NS16450 or INS8250. We don't bother to differentiate
|
|
* between them. They're too old to be interesting.
|
|
*/
|
|
uart_setreg(bas, REG_MCR, mcr);
|
|
uart_barrier(bas);
|
|
sc->sc_rxfifosz = sc->sc_txfifosz = 1;
|
|
device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
|
|
return (0);
|
|
}
|
|
|
|
uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
|
|
uart_barrier(bas);
|
|
|
|
count = 0;
|
|
delay = lpc_ns8250_delay(bas);
|
|
|
|
/* We have FIFOs. Drain the transmitter and receiver. */
|
|
error = lpc_ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
|
|
if (error) {
|
|
uart_setreg(bas, REG_MCR, mcr);
|
|
uart_setreg(bas, REG_FCR, 0);
|
|
uart_barrier(bas);
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* We should have a sufficiently clean "pipe" to determine the
|
|
* size of the FIFOs. We send as much characters as is reasonable
|
|
* and wait for the overflow bit in the LSR register to be
|
|
* asserted, counting the characters as we send them. Based on
|
|
* that count we know the FIFO size.
|
|
*/
|
|
do {
|
|
uart_setreg(bas, REG_DATA, 0);
|
|
uart_barrier(bas);
|
|
count++;
|
|
|
|
limit = 30;
|
|
lsr = 0;
|
|
/*
|
|
* LSR bits are cleared upon read, so we must accumulate
|
|
* them to be able to test LSR_OE below.
|
|
*/
|
|
while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
|
|
--limit)
|
|
DELAY(delay);
|
|
if (limit == 0) {
|
|
ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
|
|
uart_setreg(bas, REG_IER, ier);
|
|
uart_setreg(bas, REG_MCR, mcr);
|
|
uart_setreg(bas, REG_FCR, 0);
|
|
uart_barrier(bas);
|
|
count = 0;
|
|
goto done;
|
|
}
|
|
} while ((lsr & LSR_OE) == 0 && count < 130);
|
|
count--;
|
|
|
|
uart_setreg(bas, REG_MCR, mcr);
|
|
|
|
/* Reset FIFOs. */
|
|
lpc_ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
|
|
|
|
done:
|
|
sc->sc_rxfifosz = 64;
|
|
device_set_desc(sc->sc_dev, "LPC32x0 UART with FIFOs");
|
|
|
|
/*
|
|
* Force the Tx FIFO size to 16 bytes for now. We don't program the
|
|
* Tx trigger. Also, we assume that all data has been sent when the
|
|
* interrupt happens.
|
|
*/
|
|
sc->sc_txfifosz = 16;
|
|
|
|
#if 0
|
|
/*
|
|
* XXX there are some issues related to hardware flow control and
|
|
* it's likely that uart(4) is the cause. This basicly needs more
|
|
* investigation, but we avoid using for hardware flow control
|
|
* until then.
|
|
*/
|
|
/* 16650s or higher have automatic flow control. */
|
|
if (sc->sc_rxfifosz > 16) {
|
|
sc->sc_hwiflow = 1;
|
|
sc->sc_hwoflow = 1;
|
|
}
|
|
#endif
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
lpc_ns8250_bus_receive(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
int xc;
|
|
uint8_t lsr;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
lsr = uart_getreg(bas, REG_LSR);
|
|
while (lsr & LSR_RXRDY) {
|
|
if (uart_rx_full(sc)) {
|
|
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
|
|
break;
|
|
}
|
|
xc = uart_getreg(bas, REG_DATA);
|
|
if (lsr & LSR_FE)
|
|
xc |= UART_STAT_FRAMERR;
|
|
if (lsr & LSR_PE)
|
|
xc |= UART_STAT_PARERR;
|
|
uart_rx_put(sc, xc);
|
|
lsr = uart_getreg(bas, REG_LSR);
|
|
}
|
|
/* Discard everything left in the Rx FIFO. */
|
|
while (lsr & LSR_RXRDY) {
|
|
(void)uart_getreg(bas, REG_DATA);
|
|
uart_barrier(bas);
|
|
lsr = uart_getreg(bas, REG_LSR);
|
|
}
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
lpc_ns8250_bus_setsig(struct uart_softc *sc, int sig)
|
|
{
|
|
struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
|
|
struct uart_bas *bas;
|
|
uint32_t new, old;
|
|
|
|
bas = &sc->sc_bas;
|
|
do {
|
|
old = sc->sc_hwsig;
|
|
new = old;
|
|
if (sig & SER_DDTR) {
|
|
SIGCHG(sig & SER_DTR, new, SER_DTR,
|
|
SER_DDTR);
|
|
}
|
|
if (sig & SER_DRTS) {
|
|
SIGCHG(sig & SER_RTS, new, SER_RTS,
|
|
SER_DRTS);
|
|
}
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
uart_lock(sc->sc_hwmtx);
|
|
lpc_ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
|
|
if (new & SER_DTR)
|
|
lpc_ns8250->mcr |= MCR_DTR;
|
|
if (new & SER_RTS)
|
|
lpc_ns8250->mcr |= MCR_RTS;
|
|
uart_setreg(bas, REG_MCR, lpc_ns8250->mcr);
|
|
uart_barrier(bas);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
lpc_ns8250_bus_transmit(struct uart_softc *sc)
|
|
{
|
|
struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
|
|
struct uart_bas *bas;
|
|
int i;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
|
|
;
|
|
uart_setreg(bas, REG_IER, lpc_ns8250->ier | IER_ETXRDY);
|
|
uart_barrier(bas);
|
|
for (i = 0; i < sc->sc_txdatasz; i++) {
|
|
uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
|
|
uart_barrier(bas);
|
|
}
|
|
sc->sc_txbusy = 1;
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|