57dc2664ef
number of banks, rows and columns the SDRAMC is programmed to access to determine the RAM size for the board, rather than hard-wiring it to be 32MB. My company's board with 64MB now probes correctly, as does the KB9202 with only 32MB. This means that to detect the right memory size, our boot loader must correctly initialize these values. This is a fairly safe assumption because the boot loader has to initialize SDRAM already, and it isn't really possible to change this register after we've accessed SDRAM.
385 lines
15 KiB
C
385 lines
15 KiB
C
/*-
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* Copyright (c) 2005 Olivier Houchard. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef AT91RM92REG_H_
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#define AT91RM92REG_H_
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/*
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* Memory map, from datasheet :
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* 0x00000000 - 0x0ffffffff : Internal Memories
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* 0x10000000 - 0x1ffffffff : Chip Select 0
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* 0x20000000 - 0x2ffffffff : Chip Select 1
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* 0x30000000 - 0x3ffffffff : Chip Select 2
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* 0x40000000 - 0x4ffffffff : Chip Select 3
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* 0x50000000 - 0x5ffffffff : Chip Select 4
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* 0x60000000 - 0x6ffffffff : Chip Select 5
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* 0x70000000 - 0x7ffffffff : Chip Select 6
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* 0x80000000 - 0x8ffffffff : Chip Select 7
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* 0x90000000 - 0xeffffffff : Undefined (Abort)
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* 0xf0000000 - 0xfffffffff : Peripherals
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*/
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#define AT91RM92_BASE 0xf0000000
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/* Usart */
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#define AT91RM92_USART0_BASE 0xffc0000
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#define AT91RM92_USART0_PDC 0xffc0100
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#define AT91RM92_USART1_BASE 0xffc4000
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#define AT91RM92_USART1_PDC 0xffc4100
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#define AT91RM92_USART2_BASE 0xffc8000
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#define AT91RM92_USART2_PDC 0xffc8100
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#define AT91RM92_USART3_BASE 0xffcc000
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#define AT91RM92_USART3_PDC 0xffcc100
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#define AT91RM92_USART_SIZE 0x4000
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/* System Registers */
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#define AT91RM92_SYS_BASE 0xffff000
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#define AT91RM92_SYS_SIZE 0x1000
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/* Interrupt Controller */
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#define IC_SMR (0) /* Source mode register */
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#define IC_SVR (128) /* Source vector register */
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#define IC_IVR (256) /* IRQ vector register */
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#define IC_FVR (260) /* FIQ vector register */
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#define IC_ISR (264) /* Interrupt status register */
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#define IC_IPR (268) /* Interrupt pending register */
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#define IC_IMR (272) /* Interrupt status register */
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#define IC_CISR (276) /* Core interrupt status register */
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#define IC_IECR (288) /* Interrupt enable command register */
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#define IC_IDCR (292) /* Interrupt disable command register */
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#define IC_ICCR (296) /* Interrupt clear command register */
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#define IC_ISCR (300) /* Interrupt set command register */
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#define IC_EOICR (304) /* End of interrupt command register */
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#define IC_SPU (308) /* Spurious vector register */
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#define IC_DCR (312) /* Debug control register */
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#define IC_FFER (320) /* Fast forcing enable register */
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#define IC_FFDR (324) /* Fast forcing disable register */
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#define IC_FFSR (328) /* Fast forcing status register */
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/* DBGU */
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#define DBGU 0x200
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#define DBGU_SIZE 0x200
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#define DBGU_C1R (0x200 + 64) /* Chip ID1 Register */
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#define DBGU_C2R (0x200 + 68) /* Chip ID2 Register */
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#define DBGU_FNTR (0x200 + 72) /* Force NTRST Register */
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#define PIOA_PER (0x400) /* PIO Enable Register */
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#define PIOA_PDR (0x400 + 4) /* PIO Disable Register */
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#define PIOA_PSR (0x400 + 8) /* PIO status register */
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#define PIOA_OER (0x400 + 16) /* Output enable register */
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#define PIOA_ODR (0x400 + 20) /* Output disable register */
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#define PIOA_OSR (0x400 + 24) /* Output status register */
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#define PIOA_IFER (0x400 + 32) /* Input filter enable register */
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#define PIOA_IFDR (0x400 + 36) /* Input filter disable register */
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#define PIOA_IFSR (0x400 + 40) /* Input filter status register */
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#define PIOA_SODR (0x400 + 48) /* Set output data register */
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#define PIOA_CODR (0x400 + 52) /* Clear output data register */
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#define PIOA_ODSR (0x400 + 56) /* Output data status register */
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#define PIOA_PDSR (0x400 + 60) /* Pin data status register */
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#define PIOA_IER (0x400 + 64) /* Interrupt enable register */
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#define PIOA_IDR (0x400 + 68) /* Interrupt disable register */
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#define PIOA_IMR (0x400 + 72) /* Interrupt mask register */
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#define PIOA_ISR (0x400 + 76) /* Interrupt status register */
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#define PIOA_MDER (0x400 + 80) /* Multi driver enable register */
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#define PIOA_MDDR (0x400 + 84) /* Multi driver disable register */
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#define PIOA_MDSR (0x400 + 88) /* Multi driver status register */
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#define PIOA_PPUDR (0x400 + 96) /* Pull-up disable register */
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#define PIOA_PPUER (0x400 + 100) /* Pull-up enable register */
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#define PIOA_PPUSR (0x400 + 104) /* Pad pull-up status register */
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#define PIOA_ASR (0x400 + 112) /* Select A register */
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#define PIOA_BSR (0x400 + 116) /* Select B register */
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#define PIOA_ABSR (0x400 + 120) /* AB Select status register */
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#define PIOA_OWER (0x400 + 160) /* Output Write enable register */
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#define PIOA_OWDR (0x400 + 164) /* Output write disable register */
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#define PIOA_OWSR (0x400 + 168) /* Output write status register */
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#define PIOB_PER (0x400) /* PIO Enable Register */
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#define PIOB_PDR (0x600 + 4) /* PIO Disable Register */
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#define PIOB_PSR (0x600 + 8) /* PIO status register */
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#define PIOB_OER (0x600 + 16) /* Output enable register */
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#define PIOB_ODR (0x600 + 20) /* Output disable register */
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#define PIOB_OSR (0x600 + 24) /* Output status register */
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#define PIOB_IFER (0x600 + 32) /* Input filter enable register */
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#define PIOB_IFDR (0x600 + 36) /* Input filter disable register */
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#define PIOB_IFSR (0x600 + 40) /* Input filter status register */
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#define PIOB_SODR (0x600 + 48) /* Set output data register */
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#define PIOB_CODR (0x600 + 52) /* Clear output data register */
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#define PIOB_ODSR (0x600 + 56) /* Output data status register */
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#define PIOB_PDSR (0x600 + 60) /* Pin data status register */
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#define PIOB_IER (0x600 + 64) /* Interrupt enable register */
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#define PIOB_IDR (0x600 + 68) /* Interrupt disable register */
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#define PIOB_IMR (0x600 + 72) /* Interrupt mask register */
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#define PIOB_ISR (0x600 + 76) /* Interrupt status register */
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#define PIOB_MDER (0x600 + 80) /* Multi driver enable register */
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#define PIOB_MDDR (0x600 + 84) /* Multi driver disable register */
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#define PIOB_MDSR (0x600 + 88) /* Multi driver status register */
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#define PIOB_PPUDR (0x600 + 96) /* Pull-up disable register */
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#define PIOB_PPUER (0x600 + 100) /* Pull-up enable register */
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#define PIOB_PPUSR (0x600 + 104) /* Pad pull-up status register */
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#define PIOB_ASR (0x600 + 112) /* Select A register */
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#define PIOB_BSR (0x600 + 116) /* Select B register */
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#define PIOB_ABSR (0x600 + 120) /* AB Select status register */
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#define PIOB_OWER (0x600 + 160) /* Output Write enable register */
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#define PIOB_OWDR (0x600 + 164) /* Output write disable register */
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#define PIOB_OWSR (0x600 + 168) /* Output write status register */
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#define PIOC_PER (0x800) /* PIO Enable Register */
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#define PIOC_PDR (0x800 + 4) /* PIO Disable Register */
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#define PIOC_PSR (0x800 + 8) /* PIO status register */
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#define PIOC_OER (0x800 + 16) /* Output enable register */
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#define PIOC_ODR (0x800 + 20) /* Output disable register */
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#define PIOC_OSR (0x800 + 24) /* Output status register */
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#define PIOC_IFER (0x800 + 32) /* Input filter enable register */
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#define PIOC_IFDR (0x800 + 36) /* Input filter disable register */
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#define PIOC_IFSR (0x800 + 40) /* Input filter status register */
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#define PIOC_SODR (0x800 + 48) /* Set output data register */
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#define PIOC_CODR (0x800 + 52) /* Clear output data register */
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#define PIOC_ODSR (0x800 + 56) /* Output data status register */
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#define PIOC_PDSR (0x800 + 60) /* Pin data status register */
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#define PIOC_IER (0x800 + 64) /* Interrupt enable register */
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#define PIOC_IDR (0x800 + 68) /* Interrupt disable register */
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#define PIOC_IMR (0x800 + 72) /* Interrupt mask register */
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#define PIOC_ISR (0x800 + 76) /* Interrupt status register */
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#define PIOC_MDER (0x800 + 80) /* Multi driver enable register */
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#define PIOC_MDDR (0x800 + 84) /* Multi driver disable register */
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#define PIOC_MDSR (0x800 + 88) /* Multi driver status register */
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#define PIOC_PPUDR (0x800 + 96) /* Pull-up disable register */
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#define PIOC_PPUER (0x800 + 100) /* Pull-up enable register */
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#define PIOC_PPUSR (0x800 + 104) /* Pad pull-up status register */
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#define PIOC_ASR (0x800 + 112) /* Select A register */
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#define PIOC_BSR (0x800 + 116) /* Select B register */
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#define PIOC_ABSR (0x800 + 120) /* AB Select status register */
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#define PIOC_OWER (0x800 + 160) /* Output Write enable register */
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#define PIOC_OWDR (0x800 + 164) /* Output write disable register */
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#define PIOC_OWSR (0x800 + 168) /* Output write status register */
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#define PIOD_PER (0xa00) /* PIO Enable Register */
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#define PIOD_PDR (0xa00 + 4) /* PIO Disable Register */
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#define PIOD_PSR (0xa00 + 8) /* PIO status register */
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#define PIOD_OER (0xa00 + 16) /* Output enable register */
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#define PIOD_ODR (0xa00 + 20) /* Output disable register */
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#define PIOD_OSR (0xa00 + 24) /* Output status register */
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#define PIOD_IFER (0xa00 + 32) /* Input filter enable register */
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#define PIOD_IFDR (0xa00 + 36) /* Input filter disable register */
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#define PIOD_IFSR (0xa00 + 40) /* Input filter status register */
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#define PIOD_SODR (0xa00 + 48) /* Set output data register */
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#define PIOD_CODR (0xa00 + 52) /* Clear output data register */
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#define PIOD_ODSR (0xa00 + 56) /* Output data status register */
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#define PIOD_PDSR (0xa00 + 60) /* Pin data status register */
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#define PIOD_IER (0xa00 + 64) /* Interrupt enable register */
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#define PIOD_IDR (0xa00 + 68) /* Interrupt disable register */
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#define PIOD_IMR (0xa00 + 72) /* Interrupt mask register */
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#define PIOD_ISR (0xa00 + 76) /* Interrupt status register */
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#define PIOD_MDER (0xa00 + 80) /* Multi driver enable register */
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#define PIOD_MDDR (0xa00 + 84) /* Multi driver disable register */
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#define PIOD_MDSR (0xa00 + 88) /* Multi driver status register */
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#define PIOD_PPUDR (0xa00 + 96) /* Pull-up disable register */
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#define PIOD_PPUER (0xa00 + 100) /* Pull-up enable register */
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#define PIOD_PPUSR (0xa00 + 104) /* Pad pull-up status register */
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#define PIOD_ASR (0xa00 + 112) /* Select A register */
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#define PIOD_BSR (0xa00 + 116) /* Select B register */
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#define PIOD_ABSR (0xa00 + 120) /* AB Select status register */
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#define PIOD_OWER (0xa00 + 160) /* Output Write enable register */
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#define PIOD_OWDR (0xa00 + 164) /* Output write disable register */
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#define PIOD_OWSR (0xa00 + 168) /* Output write status register */
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/*
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* PIO
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*/
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#define AT91RM92_PIOA_BASE 0xffff400
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#define AT91RM92_PIO_SIZE 0x200
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#define AT91RM92_PIOB_BASE 0xffff600
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#define AT91RM92_PIOC_BASE 0xffff800
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#define AT91RM92_PIOD_BASE 0xffffa00
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/*
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* PMC
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*/
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#define AT91RM92_PMC_BASE 0xffffc00
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#define AT91RM92_PMC_SIZE 0x100
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/* IRQs : */
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/*
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* 0: AIC
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* 1: System peripheral (System timer, RTC, DBGU)
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* 2: PIO Controller A
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* 3: PIO Controller B
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* 4: PIO Controller C
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* 5: PIO Controller D
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* 6: USART 0
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* 7: USART 1
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* 8: USART 2
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* 9: USART 3
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* 10: MMC Interface
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* 11: USB device port
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* 12: Two-wirte interface
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* 13: SPI
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* 14: SSC
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* 15: SSC
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* 16: SSC
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* 17: Timer Counter 0
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* 18: Timer Counter 1
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* 19: Timer Counter 2
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* 20: Timer Counter 3
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* 21: Timer Counter 4
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* 22: Timer Counter 6
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* 23: USB Host port
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* 24: Ethernet
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* 25: AIC
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* 26: AIC
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* 27: AIC
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* 28: AIC
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* 29: AIC
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* 30: AIC
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* 31: AIC
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*/
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#define AT91RM92_IRQ_SYSTEM 1
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#define AT91RM92_IRQ_PIOA 2
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#define AT91RM92_IRQ_PIOB 3
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#define AT91RM92_IRQ_PIOC 4
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#define AT91RM92_IRQ_PIOD 5
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#define AT91RM92_IRQ_USART0 6
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#define AT91RM92_IRQ_USART1 7
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#define AT91RM92_IRQ_USART2 8
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#define AT91RM92_IRQ_USART3 9
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#define AT91RM92_IRQ_MCI 10
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#define AT91RM92_IRQ_UDP 11
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#define AT91RM92_IRQ_TWI 12
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#define AT91RM92_IRQ_SPI 13
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#define AT91RM92_IRQ_SSC0 14
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#define AT91RM92_IRQ_SSC1 15
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#define AT91RM92_IRQ_SSC2 16
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#define AT91RM92_IRQ_TC0 17
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#define AT91RM92_IRQ_TC1 18
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#define AT91RM92_IRQ_TC2 19
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#define AT91RM92_IRQ_TC3 20
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#define AT91RM92_IRQ_TC4 21
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#define AT91RM92_IRQ_TC5 22
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#define AT91RM92_IRQ_UHP 23
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#define AT91RM92_IRQ_EMAC 24
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#define AT91RM92_IRQ_AIC_BASE 25
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/* Timer */
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#define AT91RM92_AIC_BASE 0xffff000
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#define AT91RM92_AIC_SIZE 0x200
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#define AT91RM92_DBGU_BASE 0xffff200
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#define AT91RM92_DBGU_SIZE 0x200
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#define AT91RM92_RTC_BASE 0xffffe00
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#define AT91RM92_RTC_SIZE 0x100
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#define AT91RM92_MC_BASE 0xfffff00
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#define AT91RM92_MC_SIZE 0x100
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#define AT91RM92_ST_BASE 0xffffd00
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#define AT91RM92_ST_SIZE 0x100
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#define AT91RM92_SPI_BASE 0xffe0000
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#define AT91RM92_SPI_SIZE 0x4000
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#define AT91RM92_SPI_PDC 0xffe0100
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#define AT91RM92_SSC0_BASE 0xffd0000
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#define AT91RM92_SSC0_PDC 0xffd0100
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#define AT91RM92_SSC1_BASE 0xffd4000
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#define AT91RM92_SSC1_PDC 0xffd4100
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#define AT91RM92_SSC2_BASE 0xffd8000
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#define AT91RM92_SSC2_PDC 0xffd8100
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#define AT91RM92_SSC_SIZE 0x4000
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#define AT91RM92_EMAC_BASE 0xffbc000
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#define AT91RM92_EMAC_SIZE 0x4000
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#define AT91RM92_TWI_BASE 0xffb8000
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#define AT91RM92_TWI_SIZE 0x4000
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#define AT91RM92_MCI_BASE 0xffb4000
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#define AT91RM92_MCI_PDC 0xffb4100
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#define AT91RM92_MCI_SIZE 0x4000
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#define AT91RM92_UDP_BASE 0xffb0000
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#define AT91RM92_UDP_SIZE 0x4000
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#define AT91RM92_TC0_BASE 0xffa0000
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#define AT91RM92_TC_SIZE 0x4000
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#define AT91RM92_TC0C0_BASE 0xffa0000
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#define AT91RM92_TC0C1_BASE 0xffa0040
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#define AT91RM92_TC0C2_BASE 0xffa0080
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#define AT91RM92_TC1_BASE 0xffa4000
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#define AT91RM92_TC1C0_BASE 0xffa4000
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#define AT91RM92_TC1C1_BASE 0xffa4040
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#define AT91RM92_TC1C2_BASE 0xffa4080
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#define AT91RM92_OHCI_BASE 0x00300000
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#define AT91RM92_OHCI_SIZE 0x00100000
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#define AT91C_MASTER_CLOCK 60000000
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/* SDRAMC */
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#define AT91RM92_SDRAMC_BASE 0xfffff90
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#define AT91RM92_SDRAMC_MR 0x00
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#define AT91RM92_SDRAMC_MR_MODE_NORMAL 0
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#define AT91RM92_SDRAMC_MR_MODE_NOP 1
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#define AT91RM92_SDRAMC_MR_MODE_PRECHARGE 2
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#define AT91RM92_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
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#define AT91RM92_SDRAMC_MR_MODE_REFRESH 4
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#define AT91RM92_SDRAMC_MR_DBW_16 0x10
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#define AT91RM92_SDRAMC_TR 0x04
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#define AT91RM92_SDRAMC_CR 0x08
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#define AT91RM92_SDRAMC_CR_NC_8 0x0
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#define AT91RM92_SDRAMC_CR_NC_9 0x1
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#define AT91RM92_SDRAMC_CR_NC_10 0x2
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#define AT91RM92_SDRAMC_CR_NC_11 0x3
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#define AT91RM92_SDRAMC_CR_NC_MASK 0x00000003
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#define AT91RM92_SDRAMC_CR_NR_11 0x0
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#define AT91RM92_SDRAMC_CR_NR_12 0x4
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#define AT91RM92_SDRAMC_CR_NR_13 0x8
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#define AT91RM92_SDRAMC_CR_NR_RES 0xc
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#define AT91RM92_SDRAMC_CR_NR_MASK 0x0000000c
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#define AT91RM92_SDRAMC_CR_NB_2 0x00
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#define AT91RM92_SDRAMC_CR_NB_4 0x10
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#define AT91RM92_SDRAMC_CR_NB_MASK 0x00000010
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#define AT91RM92_SDRAMC_CR_NCAS_MASK 0x00000060
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#define AT91RM92_SDRAMC_CR_TWR_MASK 0x00000780
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#define AT91RM92_SDRAMC_CR_TRC_MASK 0x00007800
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#define AT91RM92_SDRAMC_CR_TRP_MASK 0x00078000
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#define AT91RM92_SDRAMC_CR_TRCD_MASK 0x00780000
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#define AT91RM92_SDRAMC_CR_TRAS_MASK 0x07800000
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#define AT91RM92_SDRAMC_CR_TXSR_MASK 0x78000000
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#define AT91RM92_SDRAMC_SRR 0x0c
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#define AT91RM92_SDRAMC_LPR 0x10
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#define AT91RM92_SDRAMC_IER 0x14
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#define AT91RM92_SDRAMC_IDR 0x18
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#define AT91RM92_SDRAMC_IMR 0x1c
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#define AT91RM92_SDRAMC_ISR 0x20
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#define AT91RM92_SDRAMC_IER_RES 0x1
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#endif /* AT91RM92REG_H_ */
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