0d4a4b1301
From git://xenbits.xen.org/people/ianc/device-tree-rebasing.git
commit efa963ec806366c9628dfd1269316bb93b7ecb15
Merge: a72ba09 459c249
Author: Ian Campbell <ian.campbell@citrix.com>
Date: Wed Feb 26 08:39:16 2014 +0000
Merge tag 'v3.14-rc4-dts'
Linux 3.14-rc4
25 lines
660 B
Plaintext
25 lines
660 B
Plaintext
NVIDIA Tegra20 timer
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The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
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running counter. The first two channels may also trigger a watchdog reset.
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Required properties:
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- compatible : should be "nvidia,tegra20-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 4 interrupts; one per timer channel.
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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Example:
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timer {
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compatible = "nvidia,tegra20-timer";
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reg = <0x60005000 0x60>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04>;
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clocks = <&tegra_car 132>;
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};
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