279 lines
7.2 KiB
C
279 lines
7.2 KiB
C
/*-
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* Copyright (C) 2013 Ian Lepore.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Atmel at91-family integrated NAND controller driver.
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*
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* This code relies on the board setup code (in at91/board_whatever.c) having
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* set up the EBI and SMC registers appropriately for whatever type of nand part
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* is on the board.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/time.h>
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#include <machine/bus.h>
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#include <dev/nand/nand.h>
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#include <dev/nand/nandbus.h>
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#include "nfc_if.h"
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#include <dev/nand/nfc_at91.h>
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#include <arm/at91/at91_smc.h>
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/*
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* Data cycles are triggered by access to any address within the EBI CS3 region
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* that has A21 and A22 clear. Command cycles are any access with bit A21
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* asserted. Address cycles are any access with bit A22 asserted. Or vice versa.
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* We get these parameters from the nand_param that the board is required to
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* call at91_enable_nand, and enable the GPIO lines properly (that will be moved
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* into at91_enable_nand when the great GPIO pin renumbering happens). We use
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* ale (Address Latch Enable) and cle (Comand Latch Enable) to match the hardware
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* names used in NAND.
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*/
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#define AT91_NAND_DATA 0
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struct at91_nand_softc {
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struct nand_softc nand_sc;
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struct resource *res;
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struct at91_nand_params *nand_param;
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};
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static struct at91_nand_params nand_param;
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static int at91_nand_attach(device_t);
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static int at91_nand_probe(device_t);
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static uint8_t at91_nand_read_byte(device_t);
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static void at91_nand_read_buf(device_t, void *, uint32_t);
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static int at91_nand_read_rnb(device_t);
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static int at91_nand_select_cs(device_t, uint8_t);
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static int at91_nand_send_command(device_t, uint8_t);
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static int at91_nand_send_address(device_t, uint8_t);
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static void at91_nand_write_buf(device_t, void *, uint32_t);
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void
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at91_enable_nand(const struct at91_nand_params *np)
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{
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nand_param = *np;
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}
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static inline u_int8_t
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dev_read_1(struct at91_nand_softc *sc, bus_size_t offset)
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{
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return bus_read_1(sc->res, offset);
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}
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static inline void
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dev_write_1(struct at91_nand_softc *sc, bus_size_t offset, u_int8_t value)
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{
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bus_write_1(sc->res, offset, value);
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}
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static int
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at91_nand_probe(device_t dev)
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{
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device_set_desc(dev, "AT91 Integrated NAND controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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at91_nand_attach(device_t dev)
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{
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struct at91_nand_softc *sc;
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int err, rid;
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sc = device_get_softc(dev);
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sc->nand_param = &nand_param;
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if (sc->nand_param->width != 8 && sc->nand_param->width != 16) {
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device_printf(dev, "Bad bus width (%d) defaulting to 8 bits\n",
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sc->nand_param->width);
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sc->nand_param->width = 8;
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}
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at91_ebi_enable(sc->nand_param->cs);
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rid = 0;
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sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->res == NULL) {
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device_printf(dev, "could not allocate resources!\n");
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return (ENXIO);
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}
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nand_init(&sc->nand_sc, dev, NAND_ECC_SOFT, 0, 0, NULL, NULL);
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err = nandbus_create(dev);
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return (err);
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}
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static int
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at91_nand_send_command(device_t dev, uint8_t command)
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{
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struct at91_nand_softc *sc;
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nand_debug(NDBG_DRV,"at91_nand_send_command: 0x%02x", command);
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sc = device_get_softc(dev);
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dev_write_1(sc, sc->nand_param->cle, command);
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return (0);
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}
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static int
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at91_nand_send_address(device_t dev, uint8_t addr)
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{
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struct at91_nand_softc *sc;
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nand_debug(NDBG_DRV,"at91_nand_send_address: x%02x", addr);
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sc = device_get_softc(dev);
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dev_write_1(sc, sc->nand_param->ale, addr);
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return (0);
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}
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static uint8_t
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at91_nand_read_byte(device_t dev)
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{
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struct at91_nand_softc *sc;
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uint8_t data;
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sc = device_get_softc(dev);
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data = dev_read_1(sc, AT91_NAND_DATA);
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nand_debug(NDBG_DRV,"at91_nand_read_byte: 0x%02x", data);
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return (data);
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}
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static void
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at91_nand_dump_buf(const char *op, void* buf, uint32_t len)
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{
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int i;
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uint8_t *b = buf;
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printf("at91_nand_%s_buf (hex):", op);
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for (i = 0; i < len; i++) {
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if ((i & 0x01f) == 0)
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printf("\n");
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printf(" %02x", b[i]);
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}
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printf("\n");
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}
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static void
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at91_nand_read_buf(device_t dev, void* buf, uint32_t len)
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{
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struct at91_nand_softc *sc;
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sc = device_get_softc(dev);
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bus_read_multi_1(sc->res, AT91_NAND_DATA, buf, len);
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if (nand_debug_flag & NDBG_DRV)
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at91_nand_dump_buf("read", buf, len);
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}
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static void
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at91_nand_write_buf(device_t dev, void* buf, uint32_t len)
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{
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struct at91_nand_softc *sc;
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sc = device_get_softc(dev);
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if (nand_debug_flag & NDBG_DRV)
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at91_nand_dump_buf("write", buf, len);
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bus_write_multi_1(sc->res, AT91_NAND_DATA, buf, len);
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}
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static int
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at91_nand_select_cs(device_t dev, uint8_t cs)
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{
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if (cs > 0)
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return (ENODEV);
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return (0);
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}
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static int
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at91_nand_read_rnb(device_t dev)
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{
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#if 0
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/*
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* XXX There's no way for this code to know which GPIO pin (if any) is
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* attached to the chip's RNB line. Not to worry, nothing calls this;
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* at higher layers, all the nand code uses status commands.
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*/
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uint32_t bits;
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bits = at91_pio_gpio_get(AT91RM92_PIOD_BASE, AT91C_PIO_PD15);
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nand_debug(NDBG_DRV,"at91_nand: read_rnb: %#x", bits);
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return (bits != 0); /* ready */
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#endif
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panic("at91_nand_read_rnb() is not implemented\n");
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return (0);
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}
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static device_method_t at91_nand_methods[] = {
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DEVMETHOD(device_probe, at91_nand_probe),
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DEVMETHOD(device_attach, at91_nand_attach),
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DEVMETHOD(nfc_send_command, at91_nand_send_command),
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DEVMETHOD(nfc_send_address, at91_nand_send_address),
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DEVMETHOD(nfc_read_byte, at91_nand_read_byte),
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DEVMETHOD(nfc_read_buf, at91_nand_read_buf),
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DEVMETHOD(nfc_write_buf, at91_nand_write_buf),
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DEVMETHOD(nfc_select_cs, at91_nand_select_cs),
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DEVMETHOD(nfc_read_rnb, at91_nand_read_rnb),
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DEVMETHOD_END
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};
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static driver_t at91_nand_driver = {
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"nand",
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at91_nand_methods,
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sizeof(struct at91_nand_softc),
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};
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static devclass_t at91_nand_devclass;
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DRIVER_MODULE(at91_nand, atmelarm, at91_nand_driver, at91_nand_devclass, 0, 0);
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