f75615f26f
drivers. The BMIPS32/BMIPS3300 cores use a register layout distinct from the MIPS74K core, and are only found on siba(4) devices. Reviewed by: mizhka Approved by: adrian (mentor) Differential Revision: https://reviews.freebsd.org/D7791
74 lines
3.2 KiB
C
74 lines
3.2 KiB
C
/*-
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* Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef _MIPS_BROADCOM_BMIPSREG_H_
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#define _MIPS_BROADCOM_BMIPSREG_H_
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/*
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* Common BMIPS32/BMIPS3300 Registers
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*/
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#define BCM_BMIPS_CORECTL 0x00 /**< core control */
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#define BCM_BMIPS_CORECTL_FORCE_RST 0x01 /**< force reset */
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#define BCM_BMIPS_CORECTL_NO_FLSH_EXC 0x02 /**< flash exception disable */
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#define BCM_BMIPS_INTR_STATUS 0x20 /**< interrupt status */
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#define BCM_BMIPS_INTR_MASK 0x24 /**< interrupt mask */
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#define BCM_BMIPS_TIMER_INTMASK 0x01 /**< timer interrupt mask */
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#define BCM_BMIPS_TIMER_CTRL 0x28 /**< timer interval (?) */
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/*
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* Broadcom BMIPS32 (BHND_COREID_MIPS)
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*/
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#define BCM_BMIPS32_CORECTL BCM_BMIPS_CORECTL
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#define BCM_BMIPS32_BIST_STATUS 0x04 /**< built-in self-test status */
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#define BCM_BMIPS32_INTR_STATUS BCM_BMIPS_INTR_STATUS
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#define BCM_BMIPS32_INTR_MASK BCM_BMIPS_INTR_MASK
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#define BCM_BMIPS32_TIMER_CTRL BCM_BMIPS_TIMER_CTRL
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/*
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* Broadcom BMIPS3300+ (BHND_COREID_MIPS33)
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*/
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#define BCM_BMIPS33_CORECTL BCM_BMIPS_CORECTL
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#define BCM_BMIPS33_BIST_CTRL 0x04 /**< build-in self-test control */
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#define BCM_BMIPS33_BIST_CTRL_DUMP 0x01 /**< BIST dump */
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#define BCM_BMIPS33_BIST_CTRL_DEBUG 0x02 /**< BIST debug */
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#define BCM_BMIPS33_BIST_CTRL_HOLD 0x04 /**< BIST hold */
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#define BCM_BMIPS33_BIST_STATUS 0x08 /**< built-in self-test status */
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#define BCM_BMIPS33_INTR_STATUS BCM_BMIPS_INTR_STATUS
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#define BCM_BMIPS33_INTR_MASK BCM_BMIPS_INTR_MASK
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#define BCM_BMIPS33_TIMER_CTRL BCM_BMIPS_TIMER_CTRL
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#define BCM_BMIPS33_TEST_MUX_SEL 0x30 /**< test multiplexer select (?) */
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#define BCM_BMIPS33_TEST_MUX_EN 0x34 /**< test multiplexer enable (?) */
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#define BCM_BMIPS33_EJTAG_GPIO_EN 0x2C /**< ejtag gpio enable */
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#endif /* _MIPS_BROADCOM_BMIPSREG_H_ */
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