5619a3e4bf
o) Add TARGET_ABI to the MIPS toolchain build process. This sets the default ABI to one of o32, n32 or n64. If it is not set, o32 is assumed as that is the current default. o) Set the default GCC cpu type to any specified TARGET_CPUTYPE. This is necessary to have a working "cc" if e.g. mips64 is specified, as binutils will refuse to link objects using different ISAs in some cases. o) Add support for n32 and n64 ABIs to binutils and GCC. o) Add additional required libgcc2 stubs for n32 and n64. o) Add support for the "mips64r2" architecture to GCC. Add the "octeon" o) When static linking, wrap default libraries in --start-group and --end-group. This is required for static linking to work on n64 with the interdependencies between libraries there. This is what other OSes that support n64 seem to do, as well. o) Fix our GCC spec to define __mips64 for 64-bit targets, not __mips64__, the former being what libgcc, etc., check and the latter seemingly being a misspelling of a hand merge from a Linux spec. o) When no TARGET_CPUTYPE is specified at build time, make GCC take the default ISA from the ABI. Our old defaults were too liberal and assumed that 64-bit ABIs should default to the MIPS64 ISA and that 32-bit ABIs should default to the MIPS32 ISA, when we are supporting or will support some systems based on earlier 32-bit and 64-bit ISAs, most notably MIPS-III. o) Merge a new opcode file (and support code) from a later version of binutils and add flags and code necessary to support Octeon-specific instructions. This should also make merging opcodes for other modern architectures easier. Reviewed by: imp
241 lines
12 KiB
C
241 lines
12 KiB
C
/* mips16-opc.c. Mips16 opcode table.
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Copyright 1996, 1997, 1998, 2000, 2005 Free Software Foundation, Inc.
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Contributed by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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1, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#include <stdio.h>
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#include "sysdep.h"
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#include "opcode/mips.h"
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/* This is the opcodes table for the mips16 processor. The format of
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this table is intentionally identical to the one in mips-opc.c.
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However, the special letters that appear in the argument string are
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different, and the table uses some different flags. */
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/* Use some short hand macros to keep down the length of the lines in
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the opcodes table. */
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#define UBD INSN_UNCOND_BRANCH_DELAY
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#define BR MIPS16_INSN_BRANCH
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#define WR_x MIPS16_INSN_WRITE_X
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#define WR_y MIPS16_INSN_WRITE_Y
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#define WR_z MIPS16_INSN_WRITE_Z
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#define WR_T MIPS16_INSN_WRITE_T
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#define WR_SP MIPS16_INSN_WRITE_SP
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#define WR_31 MIPS16_INSN_WRITE_31
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#define WR_Y MIPS16_INSN_WRITE_GPR_Y
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#define RD_x MIPS16_INSN_READ_X
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#define RD_y MIPS16_INSN_READ_Y
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#define RD_Z MIPS16_INSN_READ_Z
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#define RD_T MIPS16_INSN_READ_T
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#define RD_SP MIPS16_INSN_READ_SP
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#define RD_31 MIPS16_INSN_READ_31
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#define RD_PC MIPS16_INSN_READ_PC
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#define RD_X MIPS16_INSN_READ_GPR_X
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#define WR_HI INSN_WRITE_HI
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#define WR_LO INSN_WRITE_LO
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#define RD_HI INSN_READ_HI
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#define RD_LO INSN_READ_LO
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#define TRAP INSN_TRAP
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#define I3 INSN_ISA3
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#define T3 INSN_3900
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const struct mips_opcode mips16_opcodes[] =
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{
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{"nop", "", 0x6500, 0xffff, RD_Z, 0, 0 }, /* move $0,$Z */
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{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0, 0 },
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{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, 0 },
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{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, 0 },
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{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, 0 },
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{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, 0 },
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{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, 0 },
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{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, 0 },
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{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, 0 },
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{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0, 0 },
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{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, 0 },
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{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, 0 },
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{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, 0 },
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{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, 0 },
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{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, 0 },
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{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, 0 },
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{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, 0 },
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{"b", "q", 0x1000, 0xf800, BR, 0, 0 },
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{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, 0 },
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{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, 0 },
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{"beqz", "x,p", 0x2000, 0xf800, BR|RD_x, 0, 0 },
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{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, 0 },
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{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0, 0 },
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{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, 0 },
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{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, 0 },
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{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, 0 },
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{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO, 0, 0 },
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{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, 0 },
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{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, 0 },
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{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, 0 },
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{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO, 0, 0 },
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{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, 0 },
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{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, 0 },
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{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, 0 },
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{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO, 0, 0 },
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{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, 0 },
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{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, 0 },
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{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, 0 },
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{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0, 0 },
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{"bnez", "x,p", 0x2800, 0xf800, BR|RD_x, 0, 0 },
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{"break", "6", 0xe805, 0xf81f, TRAP, 0, 0 },
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{"bteqz", "p", 0x6000, 0xff00, BR|RD_T, 0, 0 },
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{"btnez", "p", 0x6100, 0xff00, BR|RD_T, 0, 0 },
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{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, 0 },
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{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0, 0 },
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{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, 0 },
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{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3 },
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{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3 },
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{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
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{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
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{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3 },
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{"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, 0, I3 },
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{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3 },
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{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3 },
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{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
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{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
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{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3 },
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{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
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{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, 0 },
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{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
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{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, 0 },
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{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 },
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{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, 0 },
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{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 },
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{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, 0 },
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{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
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{"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
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{"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
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{"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
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{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, 0 },
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{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
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{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, 0 },
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{"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
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{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, 0, I3 },
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{"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
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{"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
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{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, 0, I3 },
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{"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
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{"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
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{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, 0, I3 },
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{"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
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{"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, 0, I3 },
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{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO, 0, 0 },
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{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, 0 },
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{"exit", "L", 0xed09, 0xff1f, TRAP, 0, 0 },
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{"exit", "L", 0xee09, 0xff1f, TRAP, 0, 0 },
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{"exit", "L", 0xef09, 0xff1f, TRAP, 0, 0 },
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{"entry", "l", 0xe809, 0xf81f, TRAP, 0, 0 },
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{"extend", "e", 0xf000, 0xf800, 0, 0, 0 },
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{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, 0 },
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{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, 0 },
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{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, 0 },
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{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, 0 },
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{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0, 0 },
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{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31, 0, 0 },
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{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, 0 },
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{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0, 0 },
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{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, 0 },
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{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0, 0 },
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{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, 0 },
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{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, 0 },
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{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3 },
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{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, 0, I3 },
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{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0, 0 },
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{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0, 0 },
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{"li", "x,U", 0x6800, 0xf800, WR_x, 0, 0 },
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{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0, 0 },
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{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0, 0 },
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{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0, 0 },
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{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0, 0 },
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{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, 0, I3 },
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{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0, 0 },
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{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0, 0 },
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{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0, 0 },
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{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0, 0 },
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{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, 0 },
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{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 },
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{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 },
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{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0, 0 },
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{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0, 0 },
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{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0, 0 },
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{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 },
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{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, 0 },
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{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 },
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{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, 0 },
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{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0, 0 },
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{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, 0, I3 },
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{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, 0, I3 },
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{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0, 0 },
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{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0, 0 },
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{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, 0 },
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{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0, 0 },
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{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, 0 },
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{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, 0 },
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{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0, 0 },
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{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, 0 },
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{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, 0 },
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{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0, 0 },
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{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, 0 },
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{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, 0 },
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{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0, 0 },
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{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, 0 },
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{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, 0 },
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{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0, 0 },
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{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, 0 },
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{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0, 0 },
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{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO, 0, 0 },
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{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO,0, 0 },
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{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, 0 },
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{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, 0 },
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{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, 0 },
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{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, 0 },
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/* MIPS16e additions */
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{"jalrc", "x", 0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0, 0 },
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{"jalrc", "R,x", 0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0, 0 },
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{"jrc", "x", 0xe880, 0xf8ff, RD_x|TRAP, 0, 0 },
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{"jrc", "R", 0xe8a0, 0xffff, RD_31|TRAP, 0, 0 },
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{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP, 0, 0 },
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{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP, 0, 0 },
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{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, 0 },
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{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, 0 },
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{"sew", "x", 0xe8d1, 0xf8ff, WR_x|RD_x, 0, I3 },
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{"zeb", "x", 0xe811, 0xf8ff, WR_x|RD_x, 0, 0 },
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{"zeh", "x", 0xe831, 0xf8ff, WR_x|RD_x, 0, 0 },
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{"zew", "x", 0xe851, 0xf8ff, WR_x|RD_x, 0, I3 },
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|
};
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|
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const int bfd_mips16_num_opcodes =
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((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0])));
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