e113789bdc
work in FreeBSD. This is still heavily a work in progress but I'd rather it start shipping in -HEAD sooner rather than later. This doesn't (yet) link it into the build system either for a static kernel or as a module; that will come later (after many, many make universe tests.)
602 lines
19 KiB
C
602 lines
19 KiB
C
/*
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* Copyright (c) 2013 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
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* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
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* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
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* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_desc.h"
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#include "ah_internal.h"
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#include "ar9300/ar9300.h"
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#include "ar9300/ar9300phy.h"
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#include "ar9300/ar9300reg.h"
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/*
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* Default 5413/9300 radar phy parameters
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* Values adjusted to fix EV76432/EV76320
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*/
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#define AR9300_DFS_FIRPWR -28
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#define AR9300_DFS_RRSSI 0
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#define AR9300_DFS_HEIGHT 10
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#define AR9300_DFS_PRSSI 6
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#define AR9300_DFS_INBAND 8
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#define AR9300_DFS_RELPWR 8
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#define AR9300_DFS_RELSTEP 12
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#define AR9300_DFS_MAXLEN 255
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/*
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* This PRSSI value should be used during CAC.
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*/
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#define AR9300_DFS_PRSSI_CAC 10
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/*
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* make sure that value matches value in ar9300_osprey_2p2_mac_core[][2]
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* for register 0x1040 to 0x104c
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*/
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#define AR9300_DEFAULT_DIFS 0x002ffc0f
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#define AR9300_FCC_RADARS_FCC_OFFSET 4
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struct dfs_pulse ar9300_etsi_radars[] = {
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/* for short pulses, RSSI threshold should be smaller than
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* Kquick-drop. The chip has only one chance to drop the gain which
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* will be reported as the estimated RSSI */
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/* TYPE staggered pulse */
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/* 0.8-2us, 2-3 bursts,300-400 PRF, 10 pulses each */
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{30, 2, 300, 400, 2, 30, 3, 0, 5, 15, 0, 0, 1, 31}, /* Type 5*/
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/* 0.8-2us, 2-3 bursts, 400-1200 PRF, 15 pulses each */
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{30, 2, 400, 1200, 2, 30, 7, 0, 5, 15, 0, 0, 0, 32}, /* Type 6 */
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/* constant PRF based */
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/* 0.8-5us, 200 300 PRF, 10 pulses */
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{10, 5, 200, 400, 0, 24, 5, 0, 8, 15, 0, 0, 2, 33}, /* Type 1 */
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{10, 5, 400, 600, 0, 24, 5, 0, 8, 15, 0, 0, 2, 37}, /* Type 1 */
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{10, 5, 600, 800, 0, 24, 5, 0, 8, 15, 0, 0, 2, 38}, /* Type 1 */
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{10, 5, 800, 1000, 0, 24, 5, 0, 8, 15, 0, 0, 2, 39}, /* Type 1 */
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// {10, 5, 200, 1000, 0, 24, 5, 0, 8, 15, 0, 0, 2, 33},
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/* 0.8-15us, 200-1600 PRF, 15 pulses */
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{15, 15, 200, 1600, 0, 24, 8, 0, 18, 24, 0, 0, 0, 34}, /* Type 2 */
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/* 0.8-15us, 2300-4000 PRF, 25 pulses*/
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{25, 15, 2300, 4000, 0, 24, 10, 0, 18, 24, 0, 0, 0, 35}, /* Type 3 */
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/* 20-30us, 2000-4000 PRF, 20 pulses*/
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{20, 30, 2000, 4000, 0, 24, 8, 19, 33, 24, 0, 0, 0, 36}, /* Type 4 */
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};
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/* The following are for FCC Bin 1-4 pulses */
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struct dfs_pulse ar9300_fcc_radars[] = {
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/* following two filters are specific to Japan/MKK4 */
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// {18, 1, 720, 720, 1, 6, 6, 0, 1, 18, 0, 3, 0, 17}, // 1389 +/- 6 us
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// {18, 4, 250, 250, 1, 10, 5, 1, 6, 18, 0, 3, 0, 18}, // 4000 +/- 6 us
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// {18, 5, 260, 260, 1, 10, 6, 1, 6, 18, 0, 3, 0, 19}, // 3846 +/- 7 us
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{18, 1, 720, 720, 0, 6, 6, 0, 1, 18, 0, 3, 0, 17}, // 1389 +/- 6 us
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{18, 4, 250, 250, 0, 10, 5, 1, 6, 18, 0, 3, 0, 18}, // 4000 +/- 6 us
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{18, 5, 260, 260, 0, 10, 6, 1, 6, 18, 0, 3, 1, 19}, // 3846 +/- 7 us
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// {18, 5, 260, 260, 1, 10, 6, 1, 6, 18, 0, 3, 1, 20}, // 3846 +/- 7 us
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{18, 5, 260, 260, 1, 10, 6, 1, 6, 18, 0, 3, 1, 20}, // 3846 +/- 7 us
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/* following filters are common to both FCC and JAPAN */
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// FCC TYPE 1
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// {18, 1, 325, 1930, 0, 6, 7, 0, 1, 18, 0, 3, 0, 0}, // 518 to 3066
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{18, 1, 700, 700, 0, 6, 5, 0, 1, 18, 0, 3, 1, 8},
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{18, 1, 350, 350, 0, 6, 5, 0, 1, 18, 0, 3, 0, 0},
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// FCC TYPE 6
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// {9, 1, 3003, 3003, 1, 7, 5, 0, 1, 18, 0, 0, 0, 1}, // 333 +/- 7 us
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//{9, 1, 3003, 3003, 1, 7, 5, 0, 1, 18, 0, 0, 0, 1},
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{9, 1, 3003, 3003, 0, 7, 5, 0, 1, 18, 0, 0, 1, 1},
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// FCC TYPE 2
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{23, 5, 4347, 6666, 0, 18, 11, 0, 7, 22, 0, 3, 0, 2},
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// FCC TYPE 3
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{18, 10, 2000, 5000, 0, 23, 8, 6, 13, 22, 0, 3, 0, 5},
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// FCC TYPE 4
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{16, 15, 2000, 5000, 0, 25, 7, 11, 23, 22, 0, 3, 0, 11},
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};
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struct dfs_bin5pulse ar9300_bin5pulses[] = {
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{2, 28, 105, 12, 22, 5},
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};
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#if 0
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/*
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* Find the internal HAL channel corresponding to the
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* public HAL channel specified in c
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*/
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static HAL_CHANNEL_INTERNAL *
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getchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
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{
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#define CHAN_FLAGS (CHANNEL_ALL | CHANNEL_HALF | CHANNEL_QUARTER)
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HAL_CHANNEL_INTERNAL *base, *cc;
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int flags = c->channel_flags & CHAN_FLAGS;
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int n, lim;
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/*
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* Check current channel to avoid the lookup.
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*/
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cc = AH_PRIVATE(ah)->ah_curchan;
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if (cc != AH_NULL && cc->channel == c->channel &&
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(cc->channel_flags & CHAN_FLAGS) == flags) {
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return cc;
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}
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/* binary search based on known sorting order */
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base = AH_TABLES(ah)->ah_channels;
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n = AH_PRIVATE(ah)->ah_nchan;
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/* binary search based on known sorting order */
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for (lim = n; lim != 0; lim >>= 1) {
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int d;
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cc = &base[lim >> 1];
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d = c->channel - cc->channel;
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if (d == 0) {
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if ((cc->channel_flags & CHAN_FLAGS) == flags) {
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return cc;
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}
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d = flags - (cc->channel_flags & CHAN_FLAGS);
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}
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HALDEBUG(ah, HAL_DEBUG_DFS, "%s: channel %u/0x%x d %d\n", __func__,
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cc->channel, cc->channel_flags, d);
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if (d > 0) {
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base = cc + 1;
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lim--;
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}
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}
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HALDEBUG(ah, HAL_DEBUG_DFS, "%s: no match for %u/0x%x\n",
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__func__, c->channel, c->channel_flags);
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return AH_NULL;
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#undef CHAN_FLAGS
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}
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/*
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* Check the internal channel list to see if the desired channel
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* is ok to release from the NOL. If not, then do nothing. If so,
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* mark the channel as clear and reset the internal tsf time
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*/
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void
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ar9300_check_dfs(struct ath_hal *ah, struct ieee80211_channel *chan)
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{
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HAL_CHANNEL_INTERNAL *ichan = AH_NULL;
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ichan = getchannel(ah, chan);
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if (ichan == AH_NULL) {
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return;
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}
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if (!(ichan->priv_flags & CHANNEL_INTERFERENCE)) {
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return;
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}
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ichan->priv_flags &= ~CHANNEL_INTERFERENCE;
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ichan->dfs_tsf = 0;
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}
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/*
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* This function marks the channel as having found a dfs event
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* It also marks the end time that the dfs event should be cleared
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* If the channel is already marked, then tsf end time can only
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* be increased
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*/
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void
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ar9300_dfs_found(struct ath_hal *ah, struct ieee80211_channel *chan, u_int64_t nol_time)
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{
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HAL_CHANNEL_INTERNAL *ichan;
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ichan = getchannel(ah, chan);
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if (ichan == AH_NULL) {
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return;
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}
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if (!(ichan->priv_flags & CHANNEL_INTERFERENCE)) {
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ichan->dfs_tsf = ar9300_get_tsf64(ah);
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}
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ichan->dfs_tsf += nol_time;
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ichan->priv_flags |= CHANNEL_INTERFERENCE;
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chan->priv_flags |= CHANNEL_INTERFERENCE;
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}
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#endif
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/*
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* Enable radar detection and set the radar parameters per the
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* values in pe
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*/
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void
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ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
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{
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u_int32_t val;
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struct ath_hal_private *ahp = AH_PRIVATE(ah);
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const struct ieee80211_channel *chan = ahp->ah_curchan;
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struct ath_hal_9300 *ah9300 = AH9300(ah);
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int reg_writes = 0;
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val = OS_REG_READ(ah, AR_PHY_RADAR_0);
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val |= AR_PHY_RADAR_0_FFT_ENA | AR_PHY_RADAR_0_ENA;
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if (pe->pe_firpwr != HAL_PHYERR_PARAM_NOVAL) {
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val &= ~AR_PHY_RADAR_0_FIRPWR;
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val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR);
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}
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if (pe->pe_rrssi != HAL_PHYERR_PARAM_NOVAL) {
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val &= ~AR_PHY_RADAR_0_RRSSI;
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val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI);
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}
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if (pe->pe_height != HAL_PHYERR_PARAM_NOVAL) {
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val &= ~AR_PHY_RADAR_0_HEIGHT;
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val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT);
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}
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if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) {
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val &= ~AR_PHY_RADAR_0_PRSSI;
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if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
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#if 0
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if (ah->ah_use_cac_prssi) {
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val |= SM(AR9300_DFS_PRSSI_CAC, AR_PHY_RADAR_0_PRSSI);
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} else {
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#endif
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val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
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// }
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} else {
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val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
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}
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}
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if (pe->pe_inband != HAL_PHYERR_PARAM_NOVAL) {
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val &= ~AR_PHY_RADAR_0_INBAND;
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val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND);
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}
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OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
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val = OS_REG_READ(ah, AR_PHY_RADAR_1);
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val |= AR_PHY_RADAR_1_MAX_RRSSI | AR_PHY_RADAR_1_BLOCK_CHECK;
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if (pe->pe_maxlen != HAL_PHYERR_PARAM_NOVAL) {
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val &= ~AR_PHY_RADAR_1_MAXLEN;
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val |= SM(pe->pe_maxlen, AR_PHY_RADAR_1_MAXLEN);
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}
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if (pe->pe_relstep != HAL_PHYERR_PARAM_NOVAL) {
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val &= ~AR_PHY_RADAR_1_RELSTEP_THRESH;
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val |= SM(pe->pe_relstep, AR_PHY_RADAR_1_RELSTEP_THRESH);
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}
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if (pe->pe_relpwr != HAL_PHYERR_PARAM_NOVAL) {
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val &= ~AR_PHY_RADAR_1_RELPWR_THRESH;
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val |= SM(pe->pe_relpwr, AR_PHY_RADAR_1_RELPWR_THRESH);
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}
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OS_REG_WRITE(ah, AR_PHY_RADAR_1, val);
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if (ath_hal_getcapability(ah, HAL_CAP_EXT_CHAN_DFS, 0, 0) == HAL_OK) {
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val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);
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if (IEEE80211_IS_CHAN_HT40(chan)) {
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/* Enable extension channel radar detection */
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OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val | AR_PHY_RADAR_EXT_ENA);
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} else {
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/* HT20 mode, disable extension channel radar detect */
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OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val & ~AR_PHY_RADAR_EXT_ENA);
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}
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}
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/*
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apply DFS postamble array from INI
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column 0 is register ID, column 1 is HT20 value, colum2 is HT40 value
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*/
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if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_OSPREY_22(ah) || AR_SREV_SCORPION(ah)) {
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REG_WRITE_ARRAY(&ah9300->ah_ini_dfs, IEEE80211_IS_CHAN_HT40(chan)? 2:1, reg_writes);
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}
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#ifdef ATH_HAL_DFS_CHIRPING_FIX_APH128
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ath_hal_printf(ah, "DFS change the timing value\n");
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if (AR_SREV_AR9580(ah) && IEEE80211_IS_CHAN_HT40(chan)) {
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OS_REG_WRITE(ah, AR_PHY_TIMING6, 0x3140c00a);
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}
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#endif
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}
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/*
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* Get the radar parameter values and return them in the pe
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* structure
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*/
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void
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ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
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{
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u_int32_t val, temp;
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val = OS_REG_READ(ah, AR_PHY_RADAR_0);
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temp = MS(val, AR_PHY_RADAR_0_FIRPWR);
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temp |= ~(AR_PHY_RADAR_0_FIRPWR >> AR_PHY_RADAR_0_FIRPWR_S);
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pe->pe_firpwr = temp;
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pe->pe_rrssi = MS(val, AR_PHY_RADAR_0_RRSSI);
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pe->pe_height = MS(val, AR_PHY_RADAR_0_HEIGHT);
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pe->pe_prssi = MS(val, AR_PHY_RADAR_0_PRSSI);
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pe->pe_inband = MS(val, AR_PHY_RADAR_0_INBAND);
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val = OS_REG_READ(ah, AR_PHY_RADAR_1);
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pe->pe_relpwr = MS(val, AR_PHY_RADAR_1_RELPWR_THRESH);
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pe->pe_enrelpwr = !! (val & AR_PHY_RADAR_1_RELPWR_ENA);
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pe->pe_relstep = MS(val, AR_PHY_RADAR_1_RELSTEP_THRESH);
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pe->pe_en_relstep_check = !! (val & AR_PHY_RADAR_1_RELSTEP_CHECK);
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pe->pe_maxlen = MS(val, AR_PHY_RADAR_1_MAXLEN);
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}
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#if 0
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HAL_BOOL
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ar9300_radar_wait(struct ath_hal *ah, struct ieee80211_channel *chan)
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{
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struct ath_hal_private *ahp = AH_PRIVATE(ah);
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if (!ahp->ah_curchan) {
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return AH_TRUE;
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}
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/*
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* Rely on the upper layers to determine that we have spent
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* enough time waiting.
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*/
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chan->channel = ahp->ah_curchan->channel;
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chan->channel_flags = ahp->ah_curchan->channel_flags;
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chan->max_reg_tx_power = ahp->ah_curchan->max_reg_tx_power;
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ahp->ah_curchan->priv_flags |= CHANNEL_DFS_CLEAR;
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chan->priv_flags = ahp->ah_curchan->priv_flags;
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return AH_FALSE;
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}
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#endif
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struct dfs_pulse *
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ar9300_get_dfs_radars(
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struct ath_hal *ah,
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u_int32_t dfsdomain,
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int *numradars,
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struct dfs_bin5pulse **bin5pulses,
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int *numb5radars,
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HAL_PHYERR_PARAM *pe)
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{
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struct dfs_pulse *dfs_radars = AH_NULL;
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switch (dfsdomain) {
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case HAL_DFS_FCC_DOMAIN:
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dfs_radars = &ar9300_fcc_radars[AR9300_FCC_RADARS_FCC_OFFSET];
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*numradars =
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ARRAY_LENGTH(ar9300_fcc_radars) - AR9300_FCC_RADARS_FCC_OFFSET;
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*bin5pulses = &ar9300_bin5pulses[0];
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*numb5radars = ARRAY_LENGTH(ar9300_bin5pulses);
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HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_FCC_DOMAIN_9300\n", __func__);
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break;
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case HAL_DFS_ETSI_DOMAIN:
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dfs_radars = &ar9300_etsi_radars[0];
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*numradars = ARRAY_LENGTH(ar9300_etsi_radars);
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*bin5pulses = &ar9300_bin5pulses[0];
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*numb5radars = ARRAY_LENGTH(ar9300_bin5pulses);
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HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_ETSI_DOMAIN_9300\n", __func__);
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break;
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case HAL_DFS_MKK4_DOMAIN:
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dfs_radars = &ar9300_fcc_radars[0];
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*numradars = ARRAY_LENGTH(ar9300_fcc_radars);
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*bin5pulses = &ar9300_bin5pulses[0];
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*numb5radars = ARRAY_LENGTH(ar9300_bin5pulses);
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HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_MKK4_DOMAIN_9300\n", __func__);
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break;
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default:
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HALDEBUG(ah, HAL_DEBUG_DFS, "%s: no domain\n", __func__);
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return AH_NULL;
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}
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/* Set the default phy parameters per chip */
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pe->pe_firpwr = AR9300_DFS_FIRPWR;
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pe->pe_rrssi = AR9300_DFS_RRSSI;
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pe->pe_height = AR9300_DFS_HEIGHT;
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pe->pe_prssi = AR9300_DFS_PRSSI;
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/*
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we have an issue with PRSSI.
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For normal operation we use AR9300_DFS_PRSSI, which is set to 6.
|
|
Please refer to EV91563, 94164.
|
|
However, this causes problem during CAC as no radar is detected
|
|
during that period with PRSSI=6. Only PRSSI= 10 seems to fix this.
|
|
We use this flag to keep track of change in PRSSI.
|
|
*/
|
|
|
|
// ah->ah_use_cac_prssi = 0;
|
|
|
|
pe->pe_inband = AR9300_DFS_INBAND;
|
|
pe->pe_relpwr = AR9300_DFS_RELPWR;
|
|
pe->pe_relstep = AR9300_DFS_RELSTEP;
|
|
pe->pe_maxlen = AR9300_DFS_MAXLEN;
|
|
return dfs_radars;
|
|
}
|
|
|
|
void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val)
|
|
{
|
|
if (val == 0) {
|
|
/*
|
|
* EV 116936:
|
|
* Restore the register values with that of the HAL structure.
|
|
* Do not assume and overwrite these values to whatever
|
|
* is in ar9300_osprey22.ini.
|
|
*/
|
|
struct ath_hal_9300 *ahp = AH9300(ah);
|
|
HAL_TX_QUEUE_INFO *qi;
|
|
int q;
|
|
|
|
AH9300(ah)->ah_fccaifs = 0;
|
|
HALDEBUG(ah, HAL_DEBUG_DFS, "%s: restore DIFS \n", __func__);
|
|
for (q = 0; q < 4; q++) {
|
|
qi = &ahp->ah_txq[q];
|
|
OS_REG_WRITE(ah, AR_DLCL_IFS(q),
|
|
SM(qi->tqi_cwmin, AR_D_LCL_IFS_CWMIN)
|
|
| SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
|
|
| SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
|
|
}
|
|
} else {
|
|
/*
|
|
* These are values from George Lai and are specific to
|
|
* FCC domain. They are yet to be determined for other domains.
|
|
*/
|
|
|
|
AH9300(ah)->ah_fccaifs = 1;
|
|
HALDEBUG(ah, HAL_DEBUG_DFS, "%s: set DIFS to default\n", __func__);
|
|
/*printk("%s: modify DIFS\n", __func__);*/
|
|
|
|
OS_REG_WRITE(ah, AR_DLCL_IFS(0), 0x05fffc0f);
|
|
OS_REG_WRITE(ah, AR_DLCL_IFS(1), 0x05f0fc0f);
|
|
OS_REG_WRITE(ah, AR_DLCL_IFS(2), 0x05f03c07);
|
|
OS_REG_WRITE(ah, AR_DLCL_IFS(3), 0x05f01c03);
|
|
}
|
|
}
|
|
|
|
u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable)
|
|
{
|
|
u_int32_t val;
|
|
|
|
val = OS_REG_READ(ah, AR_PHY_RADAR_0);
|
|
|
|
if (is_enable) {
|
|
val |= AR_PHY_RADAR_0_FFT_ENA;
|
|
} else {
|
|
val &= ~AR_PHY_RADAR_0_FFT_ENA;
|
|
}
|
|
|
|
OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
|
|
val = OS_REG_READ(ah, AR_PHY_RADAR_0);
|
|
return val;
|
|
}
|
|
/*
|
|
function to adjust PRSSI value for CAC problem
|
|
|
|
*/
|
|
void
|
|
ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start)
|
|
{
|
|
u_int32_t val;
|
|
|
|
if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
|
|
val = OS_REG_READ(ah, AR_PHY_RADAR_0);
|
|
if (start) {
|
|
val &= ~AR_PHY_RADAR_0_PRSSI;
|
|
val |= SM(AR9300_DFS_PRSSI_CAC, AR_PHY_RADAR_0_PRSSI);
|
|
} else {
|
|
val &= ~AR_PHY_RADAR_0_PRSSI;
|
|
val |= SM(AR9300_DFS_PRSSI, AR_PHY_RADAR_0_PRSSI);
|
|
}
|
|
OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA);
|
|
// ah->ah_use_cac_prssi = start;
|
|
}
|
|
}
|
|
|
|
#if 0
|
|
struct ieee80211_channel *
|
|
ar9300_get_extension_channel(struct ath_hal *ah)
|
|
{
|
|
struct ath_hal_private *ahp = AH_PRIVATE(ah);
|
|
struct ath_hal_private_tables *aht = AH_TABLES(ah);
|
|
int i = 0;
|
|
|
|
HAL_CHANNEL_INTERNAL *ichan = AH_NULL;
|
|
CHAN_CENTERS centers;
|
|
|
|
ichan = ahp->ah_curchan;
|
|
ar9300_get_channel_centers(ah, ichan, ¢ers);
|
|
if (centers.ctl_center == centers.ext_center) {
|
|
return AH_NULL;
|
|
}
|
|
for (i = 0; i < ahp->ah_nchan; i++) {
|
|
ichan = &aht->ah_channels[i];
|
|
if (ichan->channel == centers.ext_center) {
|
|
return (struct ieee80211_channel*)ichan;
|
|
}
|
|
}
|
|
return AH_NULL;
|
|
}
|
|
#endif
|
|
|
|
HAL_BOOL
|
|
ar9300_is_fast_clock_enabled(struct ath_hal *ah)
|
|
{
|
|
struct ath_hal_private *ahp = AH_PRIVATE(ah);
|
|
|
|
if (IS_5GHZ_FAST_CLOCK_EN(ah, ahp->ah_curchan)) {
|
|
return AH_TRUE;
|
|
}
|
|
return AH_FALSE;
|
|
}
|
|
|
|
/*
|
|
* This should be enabled and linked into the build once
|
|
* radar support is enabled.
|
|
*/
|
|
#if 0
|
|
HAL_BOOL
|
|
ar9300_handle_radar_bb_panic(struct ath_hal *ah)
|
|
{
|
|
u_int32_t status;
|
|
u_int32_t val;
|
|
#ifdef AH_DEBUG
|
|
struct ath_hal_9300 *ahp = AH9300(ah);
|
|
#endif
|
|
|
|
status = AH_PRIVATE(ah)->ah_bb_panic_last_status;
|
|
|
|
if ( status == 0x04000539 ) {
|
|
/* recover from this BB panic without reset*/
|
|
/* set AR9300_DFS_FIRPWR to -1 */
|
|
val = OS_REG_READ(ah, AR_PHY_RADAR_0);
|
|
val &= (~AR_PHY_RADAR_0_FIRPWR);
|
|
val |= SM( 0x7f, AR_PHY_RADAR_0_FIRPWR);
|
|
OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
|
|
OS_DELAY(1);
|
|
/* set AR9300_DFS_FIRPWR to its default value */
|
|
val = OS_REG_READ(ah, AR_PHY_RADAR_0);
|
|
val &= ~AR_PHY_RADAR_0_FIRPWR;
|
|
val |= SM( AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR);
|
|
OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
|
|
return AH_TRUE;
|
|
} else if (status == 0x0400000a) {
|
|
/* EV 92527 : reset required if we see this signature */
|
|
HALDEBUG(ah, HAL_DEBUG_DFS, "%s: BB Panic -- 0x0400000a\n", __func__);
|
|
return AH_FALSE;
|
|
} else if (status == 0x1300000a) {
|
|
/* EV92527: we do not need a reset if we see this signature */
|
|
HALDEBUG(ah, HAL_DEBUG_DFS, "%s: BB Panic -- 0x1300000a\n", __func__);
|
|
return AH_TRUE;
|
|
} else if (AR_SREV_WASP(ah) && (status == 0x04000409)) {
|
|
return AH_TRUE;
|
|
} else {
|
|
if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK &&
|
|
(status & 0xff00000f) == 0x04000009 &&
|
|
status != 0x04000409 &&
|
|
status != 0x04000b09 &&
|
|
status != 0x04000e09 &&
|
|
(status & 0x0000ff00))
|
|
{
|
|
/* disable RIFS Rx */
|
|
#ifdef AH_DEBUG
|
|
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: BB status=0x%08x rifs=%d - disable\n",
|
|
__func__, status, ahp->ah_rifs_enabled);
|
|
ar9300_set_rifs_delay(ah, AH_FALSE);
|
|
}
|
|
return AH_FALSE;
|
|
}
|
|
}
|
|
#endif
|
|
#endif
|