875b8844be
writing event timer drivers, for choosing best possible drivers by machine independent code and for operating them to supply kernel with hardclock(), statclock() and profclock() events in unified fashion on various hardware. Infrastructure provides support for both per-CPU (independent for every CPU core) and global timers in periodic and one-shot modes. MI management code at this moment uses only periodic mode, but one-shot mode use planned for later, as part of tickless kernel project. For this moment infrastructure used on i386 and amd64 architectures. Other archs are welcome to follow, while their current operation should not be affected. This patch updates existing drivers (i8254, RTC and LAPIC) for the new order, and adds event timers support into the HPET driver. These drivers have different capabilities: LAPIC - per-CPU timer, supports periodic and one-shot operation, may freeze in C3 state, calibrated on first use, so may be not exactly precise. HPET - depending on hardware can work as per-CPU or global, supports periodic and one-shot operation, usually provides several event timers. i8254 - global, limited to periodic mode, because same hardware used also as time counter. RTC - global, supports only periodic mode, set of frequencies in Hz limited by powers of 2. Depending on hardware capabilities, drivers preferred in following orders, either LAPIC, HPETs, i8254, RTC or HPETs, LAPIC, i8254, RTC. User may explicitly specify wanted timers via loader tunables or sysctls: kern.eventtimer.timer1 and kern.eventtimer.timer2. If requested driver is unavailable or unoperational, system will try to replace it. If no more timers available or "NONE" specified for second, system will operate using only one timer, multiplying it's frequency by few times and uing respective dividers to honor hz, stathz and profhz values, set during initial setup.
123 lines
4.9 KiB
C
123 lines
4.9 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)rtc.h 7.1 (Berkeley) 5/12/91
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* $FreeBSD$
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*/
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#ifndef _I386_ISA_RTC_H_
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#define _I386_ISA_RTC_H_ 1
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/*
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* MC146818 RTC Register locations
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*/
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#define RTC_SEC 0x00 /* seconds */
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#define RTC_SECALRM 0x01 /* seconds alarm */
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#define RTC_MIN 0x02 /* minutes */
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#define RTC_MINALRM 0x03 /* minutes alarm */
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#define RTC_HRS 0x04 /* hours */
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#define RTC_HRSALRM 0x05 /* hours alarm */
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#define RTC_WDAY 0x06 /* week day */
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#define RTC_DAY 0x07 /* day of month */
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#define RTC_MONTH 0x08 /* month of year */
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#define RTC_YEAR 0x09 /* month of year */
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#define RTC_STATUSA 0x0a /* status register A */
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#define RTCSA_TUP 0x80 /* time update, don't look now */
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#define RTCSA_RESET 0x70 /* reset divider */
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#define RTCSA_DIVIDER 0x20 /* divider correct for 32768 Hz */
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#define RTCSA_8192 0x03 /* 8192 Hz interrupt */
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#define RTCSA_4096 0x04
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#define RTCSA_2048 0x05
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#define RTCSA_1024 0x06 /* default for profiling */
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#define RTCSA_PROF RTCSA_1024
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#define RTC_PROFRATE 1024
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#define RTCSA_512 0x07
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#define RTCSA_256 0x08
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#define RTCSA_128 0x09
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#define RTCSA_NOPROF RTCSA_128
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#define RTC_NOPROFRATE 128
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#define RTCSA_64 0x0a
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#define RTCSA_32 0x0b /* 32 Hz interrupt */
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#define RTC_STATUSB 0x0b /* status register B */
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#define RTCSB_DST 0x01 /* USA Daylight Savings Time enable */
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#define RTCSB_24HR 0x02 /* 0 = 12 hours, 1 = 24 hours */
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#define RTCSB_BCD 0x04 /* 0 = BCD, 1 = Binary coded time */
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#define RTCSB_SQWE 0x08 /* 1 = output sqare wave at SQW pin */
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#define RTCSB_UINTR 0x10 /* 1 = enable update-ended interrupt */
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#define RTCSB_AINTR 0x20 /* 1 = enable alarm interrupt */
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#define RTCSB_PINTR 0x40 /* 1 = enable periodic clock interrupt */
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#define RTCSB_HALT 0x80 /* stop clock updates */
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#define RTC_INTR 0x0c /* status register C (R) interrupt source */
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#define RTCIR_UPDATE 0x10 /* update intr */
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#define RTCIR_ALARM 0x20 /* alarm intr */
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#define RTCIR_PERIOD 0x40 /* periodic intr */
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#define RTCIR_INT 0x80 /* interrupt output signal */
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#define RTC_STATUSD 0x0d /* status register D (R) Lost Power */
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#define RTCSD_PWR 0x80 /* clock power OK */
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#define RTC_DIAG 0x0e /* status register E - bios diagnostic */
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#define RTCDG_BITS "\020\010clock_battery\007ROM_cksum\006config_unit\005memory_size\004fixed_disk\003invalid_time"
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#define RTC_RESET 0x0f /* status register F - reset code byte */
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#define RTCRS_RST 0x00 /* normal reset */
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#define RTCRS_LOAD 0x04 /* load system */
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#define RTC_FDISKETTE 0x10 /* diskette drive type in upper/lower nibble */
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#define RTCFDT_NONE 0 /* none present */
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#define RTCFDT_360K 0x10 /* 360K */
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#define RTCFDT_12M 0x20 /* 1.2M */
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#define RTCFDT_720K 0x30 /* 720K */
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#define RTCFDT_144M 0x40 /* 1.44M */
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#define RTCFDT_288M_1 0x50 /* 2.88M, some BIOSes */
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#define RTCFDT_288M 0x60 /* 2.88M */
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#define RTC_BASELO 0x15 /* low byte of basemem size */
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#define RTC_BASEHI 0x16 /* high byte of basemem size */
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#define RTC_EXTLO 0x17 /* low byte of extended mem size */
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#define RTC_EXTHI 0x18 /* low byte of extended mem size */
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#define RTC_CENTURY 0x32 /* current century */
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#ifdef _KERNEL
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extern struct mtx clock_lock;
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extern int atrtcclock_disable;
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int rtcin(int reg);
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void atrtc_restore(void);
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void writertc(int reg, u_char val);
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#endif
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#endif /* _I386_ISA_RTC_H_ */
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