Oleksandr Tymoshenko 8f3b7d5616 Add new quirks:
- Data timeout is broken
  - Data timeout uses SD clock
  - Capabilities register is unavailable

Add calculations for clock divisor for SDHCI 3.0
2012-10-29 17:21:58 +00:00
..
2012-10-29 17:21:58 +00:00
2012-10-29 17:21:58 +00:00