638 lines
21 KiB
C++
638 lines
21 KiB
C++
//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
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// register allocator for LLVM. This allocator works by constructing a PBQP
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// problem representing the register allocation problem under consideration,
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// solving this using a PBQP solver, and mapping the solution back to a
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// register assignment. If any variables are selected for spilling then spill
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// code is inserted and the process repeated.
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//
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// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
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// for register allocation. For more information on PBQP for register
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// allocation, see the following papers:
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//
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// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
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// PBQP. In Proceedings of the 7th Joint Modular Languages Conference
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// (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
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//
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// (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
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// architectures. In Proceedings of the Joint Conference on Languages,
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// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
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// NY, USA, 139-148.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "llvm/CodeGen/RegAllocPBQP.h"
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#include "RegisterCoalescer.h"
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#include "Spiller.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveRangeEdit.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PBQP/Graph.h"
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#include "llvm/CodeGen/PBQP/HeuristicSolver.h"
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#include "llvm/CodeGen/PBQP/Heuristics/Briggs.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include <limits>
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#include <memory>
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#include <set>
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#include <sstream>
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#include <vector>
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using namespace llvm;
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static RegisterRegAlloc
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registerPBQPRepAlloc("pbqp", "PBQP register allocator",
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createDefaultPBQPRegisterAllocator);
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static cl::opt<bool>
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pbqpCoalescing("pbqp-coalescing",
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cl::desc("Attempt coalescing during PBQP register allocation."),
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cl::init(false), cl::Hidden);
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#ifndef NDEBUG
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static cl::opt<bool>
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pbqpDumpGraphs("pbqp-dump-graphs",
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cl::desc("Dump graphs for each function/round in the compilation unit."),
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cl::init(false), cl::Hidden);
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#endif
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namespace {
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///
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/// PBQP based allocators solve the register allocation problem by mapping
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/// register allocation problems to Partitioned Boolean Quadratic
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/// Programming problems.
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class RegAllocPBQP : public MachineFunctionPass {
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public:
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static char ID;
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/// Construct a PBQP register allocator.
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RegAllocPBQP(OwningPtr<PBQPBuilder> &b, char *cPassID=0)
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: MachineFunctionPass(ID), builder(b.take()), customPassID(cPassID) {
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initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
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initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
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initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
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initializeLiveStacksPass(*PassRegistry::getPassRegistry());
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initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
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initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
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}
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/// Return the pass name.
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virtual const char* getPassName() const {
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return "PBQP Register Allocator";
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}
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/// PBQP analysis usage.
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virtual void getAnalysisUsage(AnalysisUsage &au) const;
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/// Perform register allocation
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virtual bool runOnMachineFunction(MachineFunction &MF);
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private:
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typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
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typedef std::vector<const LiveInterval*> Node2LIMap;
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typedef std::vector<unsigned> AllowedSet;
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typedef std::vector<AllowedSet> AllowedSetMap;
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typedef std::pair<unsigned, unsigned> RegPair;
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typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
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typedef std::set<unsigned> RegSet;
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OwningPtr<PBQPBuilder> builder;
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char *customPassID;
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MachineFunction *mf;
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const TargetMachine *tm;
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const TargetRegisterInfo *tri;
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const TargetInstrInfo *tii;
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const MachineLoopInfo *loopInfo;
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MachineRegisterInfo *mri;
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OwningPtr<Spiller> spiller;
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LiveIntervals *lis;
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LiveStacks *lss;
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VirtRegMap *vrm;
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RegSet vregsToAlloc, emptyIntervalVRegs;
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/// \brief Finds the initial set of vreg intervals to allocate.
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void findVRegIntervalsToAlloc();
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/// \brief Given a solved PBQP problem maps this solution back to a register
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/// assignment.
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bool mapPBQPToRegAlloc(const PBQPRAProblem &problem,
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const PBQP::Solution &solution);
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/// \brief Postprocessing before final spilling. Sets basic block "live in"
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/// variables.
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void finalizeAlloc() const;
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};
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char RegAllocPBQP::ID = 0;
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} // End anonymous namespace.
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unsigned PBQPRAProblem::getVRegForNode(PBQP::Graph::ConstNodeItr node) const {
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Node2VReg::const_iterator vregItr = node2VReg.find(node);
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assert(vregItr != node2VReg.end() && "No vreg for node.");
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return vregItr->second;
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}
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PBQP::Graph::NodeItr PBQPRAProblem::getNodeForVReg(unsigned vreg) const {
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VReg2Node::const_iterator nodeItr = vreg2Node.find(vreg);
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assert(nodeItr != vreg2Node.end() && "No node for vreg.");
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return nodeItr->second;
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}
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const PBQPRAProblem::AllowedSet&
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PBQPRAProblem::getAllowedSet(unsigned vreg) const {
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AllowedSetMap::const_iterator allowedSetItr = allowedSets.find(vreg);
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assert(allowedSetItr != allowedSets.end() && "No pregs for vreg.");
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const AllowedSet &allowedSet = allowedSetItr->second;
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return allowedSet;
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}
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unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const {
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assert(isPRegOption(vreg, option) && "Not a preg option.");
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const AllowedSet& allowedSet = getAllowedSet(vreg);
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assert(option <= allowedSet.size() && "Option outside allowed set.");
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return allowedSet[option - 1];
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}
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PBQPRAProblem *PBQPBuilder::build(MachineFunction *mf, const LiveIntervals *lis,
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const MachineLoopInfo *loopInfo,
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const RegSet &vregs) {
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LiveIntervals *LIS = const_cast<LiveIntervals*>(lis);
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MachineRegisterInfo *mri = &mf->getRegInfo();
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const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo();
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OwningPtr<PBQPRAProblem> p(new PBQPRAProblem());
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PBQP::Graph &g = p->getGraph();
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RegSet pregs;
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// Collect the set of preg intervals, record that they're used in the MF.
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for (unsigned Reg = 1, e = tri->getNumRegs(); Reg != e; ++Reg) {
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if (mri->def_empty(Reg))
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continue;
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pregs.insert(Reg);
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mri->setPhysRegUsed(Reg);
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}
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// Iterate over vregs.
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for (RegSet::const_iterator vregItr = vregs.begin(), vregEnd = vregs.end();
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vregItr != vregEnd; ++vregItr) {
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unsigned vreg = *vregItr;
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const TargetRegisterClass *trc = mri->getRegClass(vreg);
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LiveInterval *vregLI = &LIS->getInterval(vreg);
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// Record any overlaps with regmask operands.
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BitVector regMaskOverlaps;
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LIS->checkRegMaskInterference(*vregLI, regMaskOverlaps);
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// Compute an initial allowed set for the current vreg.
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typedef std::vector<unsigned> VRAllowed;
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VRAllowed vrAllowed;
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ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(*mf);
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for (unsigned i = 0; i != rawOrder.size(); ++i) {
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unsigned preg = rawOrder[i];
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if (mri->isReserved(preg))
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continue;
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// vregLI crosses a regmask operand that clobbers preg.
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if (!regMaskOverlaps.empty() && !regMaskOverlaps.test(preg))
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continue;
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// vregLI overlaps fixed regunit interference.
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bool Interference = false;
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for (MCRegUnitIterator Units(preg, tri); Units.isValid(); ++Units) {
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if (vregLI->overlaps(LIS->getRegUnit(*Units))) {
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Interference = true;
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break;
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}
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}
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if (Interference)
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continue;
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// preg is usable for this virtual register.
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vrAllowed.push_back(preg);
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}
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// Construct the node.
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PBQP::Graph::NodeItr node =
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g.addNode(PBQP::Vector(vrAllowed.size() + 1, 0));
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// Record the mapping and allowed set in the problem.
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p->recordVReg(vreg, node, vrAllowed.begin(), vrAllowed.end());
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PBQP::PBQPNum spillCost = (vregLI->weight != 0.0) ?
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vregLI->weight : std::numeric_limits<PBQP::PBQPNum>::min();
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addSpillCosts(g.getNodeCosts(node), spillCost);
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}
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for (RegSet::const_iterator vr1Itr = vregs.begin(), vrEnd = vregs.end();
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vr1Itr != vrEnd; ++vr1Itr) {
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unsigned vr1 = *vr1Itr;
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const LiveInterval &l1 = lis->getInterval(vr1);
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const PBQPRAProblem::AllowedSet &vr1Allowed = p->getAllowedSet(vr1);
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for (RegSet::const_iterator vr2Itr = llvm::next(vr1Itr);
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vr2Itr != vrEnd; ++vr2Itr) {
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unsigned vr2 = *vr2Itr;
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const LiveInterval &l2 = lis->getInterval(vr2);
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const PBQPRAProblem::AllowedSet &vr2Allowed = p->getAllowedSet(vr2);
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assert(!l2.empty() && "Empty interval in vreg set?");
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if (l1.overlaps(l2)) {
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PBQP::Graph::EdgeItr edge =
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g.addEdge(p->getNodeForVReg(vr1), p->getNodeForVReg(vr2),
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PBQP::Matrix(vr1Allowed.size()+1, vr2Allowed.size()+1, 0));
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addInterferenceCosts(g.getEdgeCosts(edge), vr1Allowed, vr2Allowed, tri);
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}
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}
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}
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return p.take();
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}
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void PBQPBuilder::addSpillCosts(PBQP::Vector &costVec,
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PBQP::PBQPNum spillCost) {
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costVec[0] = spillCost;
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}
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void PBQPBuilder::addInterferenceCosts(
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PBQP::Matrix &costMat,
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const PBQPRAProblem::AllowedSet &vr1Allowed,
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const PBQPRAProblem::AllowedSet &vr2Allowed,
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const TargetRegisterInfo *tri) {
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assert(costMat.getRows() == vr1Allowed.size() + 1 && "Matrix height mismatch.");
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assert(costMat.getCols() == vr2Allowed.size() + 1 && "Matrix width mismatch.");
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for (unsigned i = 0; i != vr1Allowed.size(); ++i) {
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unsigned preg1 = vr1Allowed[i];
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for (unsigned j = 0; j != vr2Allowed.size(); ++j) {
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unsigned preg2 = vr2Allowed[j];
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if (tri->regsOverlap(preg1, preg2)) {
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costMat[i + 1][j + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
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}
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}
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}
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}
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PBQPRAProblem *PBQPBuilderWithCoalescing::build(MachineFunction *mf,
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const LiveIntervals *lis,
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const MachineLoopInfo *loopInfo,
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const RegSet &vregs) {
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OwningPtr<PBQPRAProblem> p(PBQPBuilder::build(mf, lis, loopInfo, vregs));
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PBQP::Graph &g = p->getGraph();
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const TargetMachine &tm = mf->getTarget();
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CoalescerPair cp(*tm.getRegisterInfo());
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// Scan the machine function and add a coalescing cost whenever CoalescerPair
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// gives the Ok.
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for (MachineFunction::const_iterator mbbItr = mf->begin(),
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mbbEnd = mf->end();
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mbbItr != mbbEnd; ++mbbItr) {
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const MachineBasicBlock *mbb = &*mbbItr;
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for (MachineBasicBlock::const_iterator miItr = mbb->begin(),
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miEnd = mbb->end();
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miItr != miEnd; ++miItr) {
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const MachineInstr *mi = &*miItr;
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if (!cp.setRegisters(mi)) {
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continue; // Not coalescable.
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}
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if (cp.getSrcReg() == cp.getDstReg()) {
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continue; // Already coalesced.
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}
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unsigned dst = cp.getDstReg(),
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src = cp.getSrcReg();
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const float copyFactor = 0.5; // Cost of copy relative to load. Current
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// value plucked randomly out of the air.
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PBQP::PBQPNum cBenefit =
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copyFactor * LiveIntervals::getSpillWeight(false, true,
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loopInfo->getLoopDepth(mbb));
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if (cp.isPhys()) {
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if (!mf->getRegInfo().isAllocatable(dst)) {
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continue;
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}
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const PBQPRAProblem::AllowedSet &allowed = p->getAllowedSet(src);
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unsigned pregOpt = 0;
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while (pregOpt < allowed.size() && allowed[pregOpt] != dst) {
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++pregOpt;
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}
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if (pregOpt < allowed.size()) {
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++pregOpt; // +1 to account for spill option.
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PBQP::Graph::NodeItr node = p->getNodeForVReg(src);
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addPhysRegCoalesce(g.getNodeCosts(node), pregOpt, cBenefit);
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}
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} else {
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const PBQPRAProblem::AllowedSet *allowed1 = &p->getAllowedSet(dst);
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const PBQPRAProblem::AllowedSet *allowed2 = &p->getAllowedSet(src);
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PBQP::Graph::NodeItr node1 = p->getNodeForVReg(dst);
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PBQP::Graph::NodeItr node2 = p->getNodeForVReg(src);
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PBQP::Graph::EdgeItr edge = g.findEdge(node1, node2);
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if (edge == g.edgesEnd()) {
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edge = g.addEdge(node1, node2, PBQP::Matrix(allowed1->size() + 1,
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allowed2->size() + 1,
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0));
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} else {
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if (g.getEdgeNode1(edge) == node2) {
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std::swap(node1, node2);
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std::swap(allowed1, allowed2);
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}
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}
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addVirtRegCoalesce(g.getEdgeCosts(edge), *allowed1, *allowed2,
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cBenefit);
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}
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}
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}
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return p.take();
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}
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void PBQPBuilderWithCoalescing::addPhysRegCoalesce(PBQP::Vector &costVec,
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unsigned pregOption,
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PBQP::PBQPNum benefit) {
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costVec[pregOption] += -benefit;
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}
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void PBQPBuilderWithCoalescing::addVirtRegCoalesce(
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PBQP::Matrix &costMat,
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const PBQPRAProblem::AllowedSet &vr1Allowed,
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const PBQPRAProblem::AllowedSet &vr2Allowed,
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PBQP::PBQPNum benefit) {
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assert(costMat.getRows() == vr1Allowed.size() + 1 && "Size mismatch.");
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assert(costMat.getCols() == vr2Allowed.size() + 1 && "Size mismatch.");
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for (unsigned i = 0; i != vr1Allowed.size(); ++i) {
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unsigned preg1 = vr1Allowed[i];
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for (unsigned j = 0; j != vr2Allowed.size(); ++j) {
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unsigned preg2 = vr2Allowed[j];
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if (preg1 == preg2) {
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costMat[i + 1][j + 1] += -benefit;
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}
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}
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}
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}
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void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
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au.setPreservesCFG();
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au.addRequired<AliasAnalysis>();
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au.addPreserved<AliasAnalysis>();
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au.addRequired<SlotIndexes>();
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au.addPreserved<SlotIndexes>();
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au.addRequired<LiveIntervals>();
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au.addPreserved<LiveIntervals>();
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//au.addRequiredID(SplitCriticalEdgesID);
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if (customPassID)
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au.addRequiredID(*customPassID);
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au.addRequired<CalculateSpillWeights>();
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au.addRequired<LiveStacks>();
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au.addPreserved<LiveStacks>();
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au.addRequired<MachineDominatorTree>();
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au.addPreserved<MachineDominatorTree>();
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au.addRequired<MachineLoopInfo>();
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au.addPreserved<MachineLoopInfo>();
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au.addRequired<VirtRegMap>();
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au.addPreserved<VirtRegMap>();
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MachineFunctionPass::getAnalysisUsage(au);
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}
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void RegAllocPBQP::findVRegIntervalsToAlloc() {
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// Iterate over all live ranges.
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for (unsigned i = 0, e = mri->getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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if (mri->reg_nodbg_empty(Reg))
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continue;
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LiveInterval *li = &lis->getInterval(Reg);
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// If this live interval is non-empty we will use pbqp to allocate it.
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// Empty intervals we allocate in a simple post-processing stage in
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// finalizeAlloc.
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if (!li->empty()) {
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vregsToAlloc.insert(li->reg);
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} else {
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emptyIntervalVRegs.insert(li->reg);
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}
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}
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}
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bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAProblem &problem,
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const PBQP::Solution &solution) {
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// Set to true if we have any spills
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bool anotherRoundNeeded = false;
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// Clear the existing allocation.
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vrm->clearAllVirt();
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const PBQP::Graph &g = problem.getGraph();
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// Iterate over the nodes mapping the PBQP solution to a register
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// assignment.
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for (PBQP::Graph::ConstNodeItr node = g.nodesBegin(),
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nodeEnd = g.nodesEnd();
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node != nodeEnd; ++node) {
|
|
unsigned vreg = problem.getVRegForNode(node);
|
|
unsigned alloc = solution.getSelection(node);
|
|
|
|
if (problem.isPRegOption(vreg, alloc)) {
|
|
unsigned preg = problem.getPRegForOption(vreg, alloc);
|
|
DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> "
|
|
<< tri->getName(preg) << "\n");
|
|
assert(preg != 0 && "Invalid preg selected.");
|
|
vrm->assignVirt2Phys(vreg, preg);
|
|
} else if (problem.isSpillOption(vreg, alloc)) {
|
|
vregsToAlloc.erase(vreg);
|
|
SmallVector<LiveInterval*, 8> newSpills;
|
|
LiveRangeEdit LRE(&lis->getInterval(vreg), newSpills, *mf, *lis, vrm);
|
|
spiller->spill(LRE);
|
|
|
|
DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> SPILLED (Cost: "
|
|
<< LRE.getParent().weight << ", New vregs: ");
|
|
|
|
// Copy any newly inserted live intervals into the list of regs to
|
|
// allocate.
|
|
for (LiveRangeEdit::iterator itr = LRE.begin(), end = LRE.end();
|
|
itr != end; ++itr) {
|
|
assert(!(*itr)->empty() && "Empty spill range.");
|
|
DEBUG(dbgs() << PrintReg((*itr)->reg, tri) << " ");
|
|
vregsToAlloc.insert((*itr)->reg);
|
|
}
|
|
|
|
DEBUG(dbgs() << ")\n");
|
|
|
|
// We need another round if spill intervals were added.
|
|
anotherRoundNeeded |= !LRE.empty();
|
|
} else {
|
|
llvm_unreachable("Unknown allocation option.");
|
|
}
|
|
}
|
|
|
|
return !anotherRoundNeeded;
|
|
}
|
|
|
|
|
|
void RegAllocPBQP::finalizeAlloc() const {
|
|
// First allocate registers for the empty intervals.
|
|
for (RegSet::const_iterator
|
|
itr = emptyIntervalVRegs.begin(), end = emptyIntervalVRegs.end();
|
|
itr != end; ++itr) {
|
|
LiveInterval *li = &lis->getInterval(*itr);
|
|
|
|
unsigned physReg = mri->getSimpleHint(li->reg);
|
|
|
|
if (physReg == 0) {
|
|
const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
|
|
physReg = liRC->getRawAllocationOrder(*mf).front();
|
|
}
|
|
|
|
vrm->assignVirt2Phys(li->reg, physReg);
|
|
}
|
|
}
|
|
|
|
bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
|
|
|
|
mf = &MF;
|
|
tm = &mf->getTarget();
|
|
tri = tm->getRegisterInfo();
|
|
tii = tm->getInstrInfo();
|
|
mri = &mf->getRegInfo();
|
|
|
|
lis = &getAnalysis<LiveIntervals>();
|
|
lss = &getAnalysis<LiveStacks>();
|
|
loopInfo = &getAnalysis<MachineLoopInfo>();
|
|
|
|
vrm = &getAnalysis<VirtRegMap>();
|
|
spiller.reset(createInlineSpiller(*this, MF, *vrm));
|
|
|
|
mri->freezeReservedRegs(MF);
|
|
|
|
DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getName() << "\n");
|
|
|
|
// Allocator main loop:
|
|
//
|
|
// * Map current regalloc problem to a PBQP problem
|
|
// * Solve the PBQP problem
|
|
// * Map the solution back to a register allocation
|
|
// * Spill if necessary
|
|
//
|
|
// This process is continued till no more spills are generated.
|
|
|
|
// Find the vreg intervals in need of allocation.
|
|
findVRegIntervalsToAlloc();
|
|
|
|
#ifndef NDEBUG
|
|
const Function* func = mf->getFunction();
|
|
std::string fqn =
|
|
func->getParent()->getModuleIdentifier() + "." +
|
|
func->getName().str();
|
|
#endif
|
|
|
|
// If there are non-empty intervals allocate them using pbqp.
|
|
if (!vregsToAlloc.empty()) {
|
|
|
|
bool pbqpAllocComplete = false;
|
|
unsigned round = 0;
|
|
|
|
while (!pbqpAllocComplete) {
|
|
DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
|
|
|
|
OwningPtr<PBQPRAProblem> problem(
|
|
builder->build(mf, lis, loopInfo, vregsToAlloc));
|
|
|
|
#ifndef NDEBUG
|
|
if (pbqpDumpGraphs) {
|
|
std::ostringstream rs;
|
|
rs << round;
|
|
std::string graphFileName(fqn + "." + rs.str() + ".pbqpgraph");
|
|
std::string tmp;
|
|
raw_fd_ostream os(graphFileName.c_str(), tmp);
|
|
DEBUG(dbgs() << "Dumping graph for round " << round << " to \""
|
|
<< graphFileName << "\"\n");
|
|
problem->getGraph().dump(os);
|
|
}
|
|
#endif
|
|
|
|
PBQP::Solution solution =
|
|
PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(
|
|
problem->getGraph());
|
|
|
|
pbqpAllocComplete = mapPBQPToRegAlloc(*problem, solution);
|
|
|
|
++round;
|
|
}
|
|
}
|
|
|
|
// Finalise allocation, allocate empty ranges.
|
|
finalizeAlloc();
|
|
vregsToAlloc.clear();
|
|
emptyIntervalVRegs.clear();
|
|
|
|
DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n");
|
|
|
|
return true;
|
|
}
|
|
|
|
FunctionPass* llvm::createPBQPRegisterAllocator(
|
|
OwningPtr<PBQPBuilder> &builder,
|
|
char *customPassID) {
|
|
return new RegAllocPBQP(builder, customPassID);
|
|
}
|
|
|
|
FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
|
|
OwningPtr<PBQPBuilder> Builder;
|
|
if (pbqpCoalescing)
|
|
Builder.reset(new PBQPBuilderWithCoalescing());
|
|
else
|
|
Builder.reset(new PBQPBuilder());
|
|
return createPBQPRegisterAllocator(Builder);
|
|
}
|
|
|
|
#undef DEBUG_TYPE
|