478 lines
17 KiB
C
478 lines
17 KiB
C
/* $FreeBSD$ */
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/*
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* Copyright (c) 2000-01 Intel Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver
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*
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* Written by: Achim Leubner <achim.leubner@intel.com>
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* Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
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*
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* TODO:
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*/
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#ident "$Id: iir_pci.c 1.1 2001/05/22 20:14:12 achim Exp $"
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/* #include "opt_iir.h" */
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <machine/bus_memio.h>
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#include <machine/bus_pio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/clock.h>
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#include <sys/rman.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include <cam/scsi/scsi_all.h>
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#include <dev/iir/iir.h>
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/* Mapping registers for various areas */
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#define PCI_DPMEM PCIR_MAPS
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/* Product numbers for Fibre-Channel are greater than or equal to 0x200 */
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#define GDT_PCI_PRODUCT_FC 0x200
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/* PCI SRAM structure */
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#define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */
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#define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */
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#define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */
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#define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */
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#define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */
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#define GDT_SRAM_SZ 0x40
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/* DPRAM PCI controllers */
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#define GDT_DPR_IF 0x00 /* interface area */
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#define GDT_6SR (0xff0 - GDT_SRAM_SZ)
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#define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */
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#define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */
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#define GDT_EVENT 0xff8 /* u_int8_t, release event */
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#define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */
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#define GDT_DPRAM_SZ 0x1000
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/* PLX register structure (new PCI controllers) */
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#define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */
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#define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */
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#define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */
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#define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */
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#define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */
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#define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */
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#define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */
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#define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */
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#define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */
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#define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */
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#define GDT_PLX_SZ 0x80
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/* DPRAM new PCI controllers */
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#define GDT_IC 0x00 /* interface */
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#define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ)
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/* SRAM structure */
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#define GDT_PCINEW_SZ 0x4000
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/* i960 register structure (PCI MPR controllers) */
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#define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */
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#define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */
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#define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */
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#define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */
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#define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */
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#define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */
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#define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */
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#define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */
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#define GDT_SEVERITY 0xefc /* u_int8_t, event severity */
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#define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */
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#define GDT_I960_SZ 0x1000
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/* DPRAM PCI MPR controllers */
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#define GDT_I960R 0x00 /* 4KB i960 registers */
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#define GDT_MPR_IC GDT_I960_SZ
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/* i960 register area */
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#define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ)
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/* DPRAM struct. */
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#define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ)
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static int iir_pci_probe(device_t dev);
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static int iir_pci_attach(device_t dev);
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void gdt_pci_enable_intr(struct gdt_softc *);
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void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
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u_int8_t gdt_mpr_get_status(struct gdt_softc *);
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void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *);
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void gdt_mpr_release_event(struct gdt_softc *);
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void gdt_mpr_set_sema0(struct gdt_softc *);
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int gdt_mpr_test_busy(struct gdt_softc *);
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static device_method_t iir_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, iir_pci_probe),
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DEVMETHOD(device_attach, iir_pci_attach),
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{ 0, 0}
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};
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static driver_t iir_pci_driver =
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{
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"iir",
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iir_pci_methods,
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sizeof(struct gdt_softc)
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};
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static devclass_t iir_devclass;
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DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0);
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static int
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iir_pci_probe(device_t dev)
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{
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if (pci_get_vendor(dev) == INTEL_VENDOR_ID &&
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pci_get_device(dev) == INTEL_DEVICE_ID_IIR) {
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device_set_desc(dev, "Intel Integrated RAID Controller");
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return (0);
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}
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if (pci_get_vendor(dev) == GDT_VENDOR_ID &&
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((pci_get_device(dev) >= GDT_DEVICE_ID_MIN &&
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pci_get_device(dev) <= GDT_DEVICE_ID_MAX) ||
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pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) {
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device_set_desc(dev, "ICP Disk Array Controller");
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return (0);
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}
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return (ENXIO);
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}
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static int
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iir_pci_attach(device_t dev)
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{
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struct gdt_softc *gdt;
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struct resource *io = NULL, *irq = NULL;
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int retries, rid, error = 0;
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void *ih;
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u_int8_t protocol;
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/* map DPMEM */
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rid = PCI_DPMEM;
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io = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, RF_ACTIVE);
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if (io == NULL) {
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device_printf(dev, "can't allocate register resources\n");
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error = ENOMEM;
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goto err;
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}
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/* get IRQ */
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rid = 0;
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irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
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RF_ACTIVE | RF_SHAREABLE);
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if (io == NULL) {
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device_printf(dev, "can't find IRQ value\n");
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error = ENOMEM;
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goto err;
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}
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gdt = device_get_softc(dev);
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bzero(gdt, sizeof(struct gdt_softc));
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gdt->sc_init_level = 0;
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gdt->sc_dpmemt = rman_get_bustag(io);
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gdt->sc_dpmemh = rman_get_bushandle(io);
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gdt->sc_dpmembase = rman_get_start(io);
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gdt->sc_hanum = device_get_unit(dev);
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gdt->sc_bus = pci_get_bus(dev);
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gdt->sc_slot = pci_get_slot(dev);
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gdt->sc_device = pci_get_device(dev);
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gdt->sc_subdevice = pci_get_subdevice(dev);
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gdt->sc_class = GDT_MPR;
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/* no FC ctr.
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if (gdt->sc_device >= GDT_PCI_PRODUCT_FC)
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gdt->sc_class |= GDT_FC;
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*/
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/* initialize RP controller */
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/* check and reset interface area */
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bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC,
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htole32(GDT_MPR_MAGIC));
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if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) !=
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htole32(GDT_MPR_MAGIC)) {
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printf("cannot access DPMEM at 0x%x (shadowed?)\n",
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gdt->sc_dpmembase);
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error = ENXIO;
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goto err;
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}
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bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0),
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GDT_MPR_SZ >> 2);
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/* Disable everything */
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bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
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bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
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GDT_EDOOR_EN) | 4);
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bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
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bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
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0);
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bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX,
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0);
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bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
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htole32(gdt->sc_dpmembase));
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bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
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0xff);
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bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
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DELAY(20);
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retries = GDT_RETRIES;
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while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
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GDT_MPR_IC + GDT_S_STATUS) != 0xff) {
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if (--retries == 0) {
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printf("DEINIT failed\n");
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error = ENXIO;
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goto err;
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}
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DELAY(1);
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}
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protocol = (u_int8_t)letoh32(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
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GDT_MPR_IC + GDT_S_INFO));
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bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
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0);
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if (protocol != GDT_PROTOCOL_VERSION) {
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printf("unsupported protocol %d\n", protocol);
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error = ENXIO;
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goto err;
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}
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/* special commnd to controller BIOS */
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bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
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htole32(0));
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bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
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GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0));
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bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
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GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t),
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htole32(1));
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bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
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GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t),
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htole32(0));
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bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
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0xfe);
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bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
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DELAY(20);
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retries = GDT_RETRIES;
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while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
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GDT_MPR_IC + GDT_S_STATUS) != 0xfe) {
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if (--retries == 0) {
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printf("initialization error\n");
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error = ENXIO;
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goto err;
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}
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DELAY(1);
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}
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bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
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0);
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gdt->sc_ic_all_size = GDT_MPR_SZ;
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gdt->sc_copy_cmd = gdt_mpr_copy_cmd;
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gdt->sc_get_status = gdt_mpr_get_status;
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gdt->sc_intr = gdt_mpr_intr;
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gdt->sc_release_event = gdt_mpr_release_event;
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gdt->sc_set_sema0 = gdt_mpr_set_sema0;
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gdt->sc_test_busy = gdt_mpr_test_busy;
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/* Allocate a dmatag representing the capabilities of this attachment */
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/* XXX Should be a child of the PCI bus dma tag */
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if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0,
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/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
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/*highaddr*/BUS_SPACE_MAXADDR,
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/*filter*/NULL, /*filterarg*/NULL,
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/*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
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/*nsegments*/GDT_MAXSG,
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/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
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/*flags*/0, &gdt->sc_parent_dmat) != 0) {
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error = ENXIO;
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goto err;
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}
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gdt->sc_init_level++;
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if (iir_init(gdt) != 0) {
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iir_free(gdt);
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error = ENXIO;
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goto err;
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}
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/* Register with the XPT */
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iir_attach(gdt);
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/* associate interrupt handler */
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if (bus_setup_intr( dev, irq, INTR_TYPE_CAM,
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iir_intr, gdt, &ih )) {
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device_printf(dev, "Unable to register interrupt handler\n");
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error = ENXIO;
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goto err;
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}
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gdt_pci_enable_intr(gdt);
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return (0);
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err:
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if (irq)
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bus_release_resource( dev, SYS_RES_IRQ, 0, irq );
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/*
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if (io)
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bus_release_resource( dev, SYS_RES_MEMORY, rid, io );
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*/
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return (error);
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}
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/* Enable interrupts */
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void
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gdt_pci_enable_intr(struct gdt_softc *gdt)
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{
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GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt));
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switch(GDT_CLASS(gdt)) {
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case GDT_MPR:
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bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
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GDT_MPR_EDOOR, 0xff);
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bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
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bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
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GDT_EDOOR_EN) & ~4);
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break;
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}
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}
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/*
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* MPR PCI controller-specific functions
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*/
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void
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gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *ccb)
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{
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u_int16_t cp_count = roundup(gdt->sc_cmd_len, sizeof (u_int32_t));
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u_int16_t dp_offset = gdt->sc_cmd_off;
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u_int16_t cmd_no = gdt->sc_cmd_cnt++;
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GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt));
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gdt->sc_cmd_off += cp_count;
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bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
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GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET,
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htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset));
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bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
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GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID,
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htole16(ccb->gc_service));
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bus_space_write_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
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GDT_MPR_IC + GDT_DPR_CMD + dp_offset,
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(u_int32_t *)gdt->sc_cmd, cp_count >> 2);
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}
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u_int8_t
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gdt_mpr_get_status(struct gdt_softc *gdt)
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{
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GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt));
|
|
|
|
return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR);
|
|
}
|
|
|
|
void
|
|
gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx)
|
|
{
|
|
int i;
|
|
|
|
GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt));
|
|
|
|
if (ctx->istatus & 0x80) { /* error flag */
|
|
ctx->istatus &= ~0x80;
|
|
ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt,
|
|
gdt->sc_dpmemh, GDT_MPR_STATUS);
|
|
} else /* no error */
|
|
ctx->cmd_status = GDT_S_OK;
|
|
|
|
ctx->info =
|
|
bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO);
|
|
ctx->service =
|
|
bus_space_read_2(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SERVICE);
|
|
ctx->info2 =
|
|
bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
|
|
GDT_MPR_INFO + sizeof (u_int32_t));
|
|
|
|
/* event string */
|
|
if (ctx->istatus == GDT_ASYNCINDEX) {
|
|
if (ctx->service != GDT_SCREENSERVICE &&
|
|
(gdt->sc_fw_vers & 0xff) >= 0x1a) {
|
|
gdt->sc_dvr.severity =
|
|
bus_space_read_1(gdt->sc_dpmemt,gdt->sc_dpmemh, GDT_SEVERITY);
|
|
for (i = 0; i < 256; ++i) {
|
|
gdt->sc_dvr.event_string[i] =
|
|
bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
|
|
GDT_EVT_BUF + i);
|
|
if (gdt->sc_dvr.event_string[i] == 0)
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
|
|
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0);
|
|
}
|
|
|
|
void
|
|
gdt_mpr_release_event(struct gdt_softc *gdt)
|
|
{
|
|
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt));
|
|
|
|
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
|
|
}
|
|
|
|
void
|
|
gdt_mpr_set_sema0(struct gdt_softc *gdt)
|
|
{
|
|
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt));
|
|
|
|
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1);
|
|
}
|
|
|
|
int
|
|
gdt_mpr_test_busy(struct gdt_softc *gdt)
|
|
{
|
|
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt));
|
|
|
|
return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
|
|
GDT_MPR_SEMA0) & 1);
|
|
}
|